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| author | Eran Harary <eran.harary@intel.com> | 2013-12-02 12:18:10 +0200 |
|---|---|---|
| committer | Emmanuel Grumbach <emmanuel.grumbach@intel.com> | 2014-02-03 22:23:32 +0200 |
| commit | e12ba844acc0cc212adef6c2d5f9251ea787c822 (patch) | |
| tree | 73d41416bdf12beb9f66202ff882463e9269fff1 | |
| parent | 3073d8c0c51c0b766d35ae3beb6b29948be2ee00 (diff) | |
| download | op-kernel-dev-e12ba844acc0cc212adef6c2d5f9251ea787c822.zip op-kernel-dev-e12ba844acc0cc212adef6c2d5f9251ea787c822.tar.gz | |
iwlwifi: pcie: change CSR reset in family 8000
This register is not present in 8000 family devices.
There is prph register instead.
Signed-off-by: Eran Harary <eran.harary@intel.com>
Reviewed-by: Dor Shaish <dor.shaish@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
| -rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-prph.h | 7 | ||||
| -rw-r--r-- | drivers/net/wireless/iwlwifi/pcie/trans.c | 6 |
2 files changed, 13 insertions, 0 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h index 100bd0d..fc3b6be 100644 --- a/drivers/net/wireless/iwlwifi/iwl-prph.h +++ b/drivers/net/wireless/iwlwifi/iwl-prph.h @@ -105,6 +105,13 @@ /* Device NMI register */ #define DEVICE_SET_NMI_REG 0x00a01c30 +/* + * Device reset for family 8000 + * write to bit 24 in order to reset the CPU +*/ +#define RELEASE_CPU_RESET (0x300C) +#define RELEASE_CPU_RESET_BIT BIT(24) + /***************************************************************************** * 7000/3000 series SHR DTS addresses * *****************************************************************************/ diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c index f7e85d3..53a3457 100644 --- a/drivers/net/wireless/iwlwifi/pcie/trans.c +++ b/drivers/net/wireless/iwlwifi/pcie/trans.c @@ -573,6 +573,12 @@ static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, } } + /* release CPU reset */ + if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) + iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); + else + iwl_write32(trans, CSR_RESET, 0); + return 0; } |
