diff options
| author | Giuseppe CAVALLARO <peppe.cavallaro@st.com> | 2010-09-17 03:23:41 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-09-17 16:12:57 -0700 |
| commit | c629882ac73cab2cd41d9948caeed633fc570fc0 (patch) | |
| tree | 2dfa1375309b3238e7a2ebbe577ce1fb6eb2f2c4 | |
| parent | ebbb293f8b3021ae2009fcb7cb3b8a52fb5fd06a (diff) | |
| download | op-kernel-dev-c629882ac73cab2cd41d9948caeed633fc570fc0.zip op-kernel-dev-c629882ac73cab2cd41d9948caeed633fc570fc0.tar.gz | |
stmmac: prevent dma init stuck in case of failures.
Add a limit when perform the DMA reset procedure
so, in case of problems (i.e. PHY reset failed) the
Kernel won't hang on the stmmac DMA initialisation
blocking the Kernels execution.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/stmmac/dwmac1000_dma.c | 10 | ||||
| -rw-r--r-- | drivers/net/stmmac/dwmac100_dma.c | 10 |
2 files changed, 18 insertions, 2 deletions
diff --git a/drivers/net/stmmac/dwmac1000_dma.c b/drivers/net/stmmac/dwmac1000_dma.c index 2ef5a56..ce6163e3 100644 --- a/drivers/net/stmmac/dwmac1000_dma.c +++ b/drivers/net/stmmac/dwmac1000_dma.c @@ -33,10 +33,18 @@ static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx, u32 dma_rx) { u32 value = readl(ioaddr + DMA_BUS_MODE); + int limit; + /* DMA SW reset */ value |= DMA_BUS_MODE_SFT_RESET; writel(value, ioaddr + DMA_BUS_MODE); - do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)); + limit = 15000; + while (limit--) { + if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) + break; + } + if (limit < 0) + return -EBUSY; value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL | ((pbl << DMA_BUS_MODE_PBL_SHIFT) | diff --git a/drivers/net/stmmac/dwmac100_dma.c b/drivers/net/stmmac/dwmac100_dma.c index c7279d2b..96aac93 100644 --- a/drivers/net/stmmac/dwmac100_dma.c +++ b/drivers/net/stmmac/dwmac100_dma.c @@ -35,10 +35,18 @@ static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx, u32 dma_rx) { u32 value = readl(ioaddr + DMA_BUS_MODE); + int limit; + /* DMA SW reset */ value |= DMA_BUS_MODE_SFT_RESET; writel(value, ioaddr + DMA_BUS_MODE); - do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)); + limit = 15000; + while (limit--) { + if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) + break; + } + if (limit < 0) + return -EBUSY; /* Enable Application Access by writing to DMA CSR0 */ writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT), |
