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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2014-07-04 11:50:30 -0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-07-23 07:05:32 +0200
commitc5107b875a84f0b25d1d6b8fbc9acb22440b746f (patch)
treed452c972e288b7aa6356648be99f9fff92c73031
parent813bde438c575e2c84eed9702143d915702847e3 (diff)
downloadop-kernel-dev-c5107b875a84f0b25d1d6b8fbc9acb22440b746f.zip
op-kernel-dev-c5107b875a84f0b25d1d6b8fbc9acb22440b746f.tar.gz
drm/i915: HSW_BLC_PWM2_CTL doesn't exist on BDW
So don't write it, otherwise we will trigger unclaimed register errors. Testcase: igt/pm_rpm/rte Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9064dd9..06566d6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7326,8 +7326,9 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
"CPU PWM1 enabled\n");
- WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
- "CPU PWM2 enabled\n");
+ if (IS_HASWELL(dev))
+ WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
+ "CPU PWM2 enabled\n");
WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
"PCH PWM1 enabled\n");
WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
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