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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-10-10 23:14:01 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-10-12 10:59:10 +0200
commit9169d3a88072b20f42e68a946e916bd7dfbc7f2c (patch)
treef981fbb98946aef615546c68fced4870c07c9ff7
parent1cf8378906b2d5a6449147914fe04c56d6f4fd87 (diff)
downloadop-kernel-dev-9169d3a88072b20f42e68a946e916bd7dfbc7f2c.zip
op-kernel-dev-9169d3a88072b20f42e68a946e916bd7dfbc7f2c.tar.gz
drm/i915: disable wc gtt pte mappings on gen2
It doesn't work since the gtt pte range sits in the middle of the mmio bar. We didn't notice that since both my and Chris' gen2 machines don't support PAT and hence all wc io mapping request will automatically be demoted to uc. This regression has been introduce in commit edef7e685da05c13cce50c0126189c80fe2c8f71 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Fri Sep 14 11:57:47 2012 +0100 agp/intel: Use a write-combining map for updating PTEs Reported-by: Egbert Eich <eich@pdx.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55834 Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/char/agp/intel-gtt.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index e01f5ea..38390f7 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -667,7 +667,7 @@ static int intel_gtt_init(void)
gtt_map_size = intel_private.base.gtt_total_entries * 4;
intel_private.gtt = NULL;
- if (INTEL_GTT_GEN < 6)
+ if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2)
intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
gtt_map_size);
if (intel_private.gtt == NULL)
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