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authorFabio Estevam <fabio.estevam@freescale.com>2013-10-04 13:15:26 -0300
committerShawn Guo <shawn.guo@linaro.org>2013-10-06 19:53:09 +0800
commit8d4a54af47ce7a71fd049a942cb2ea0041b18ecb (patch)
treed6d6c879f7878b1c67cc540a8ad75b009d84841e
parente0ec2f39ef9905a24d5d88238eda3dabb8d591e0 (diff)
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op-kernel-dev-8d4a54af47ce7a71fd049a942cb2ea0041b18ecb.tar.gz
ARM: dts: imx53-qsb: SDHC3 is connected in 8-bit mode
SDHC3 is 8 bit-wide, so pass the bus-width property to reflect that. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 94597c3..b646ef1 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -136,6 +136,7 @@
pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
+ bus-width = <8>;
status = "okay";
};
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