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authorAbhishek Sahu <absahu@codeaurora.org>2016-11-25 21:11:32 +0530
committerStephen Boyd <sboyd@codeaurora.org>2016-12-21 15:57:29 -0800
commit86c654d41a52e3d17e9bc2c2ba37f3c963e66a4a (patch)
treecf32fa11f79f513b1d17f75021ad5005af4ca43e
parentb52a0c2c11401a8f39b4fcb0b59baf0059902a98 (diff)
downloadop-kernel-dev-86c654d41a52e3d17e9bc2c2ba37f3c963e66a4a.zip
op-kernel-dev-86c654d41a52e3d17e9bc2c2ba37f3c963e66a4a.tar.gz
clk: qcom: ipq4019: Add all the frequencies for apss cpu
The APSS CPU clock does not contain all the frequencies in its frequency table so this patch adds the same. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
-rw-r--r--drivers/clk/qcom/gcc-ipq4019.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 62a36e0..b87297b 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -568,10 +568,20 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
};
static const struct freq_tbl ftbl_gcc_apps_clk[] = {
- F(48000000, P_XO, 1, 0, 0),
+ F(48000000, P_XO, 1, 0, 0),
F(200000000, P_FEPLL200, 1, 0, 0),
+ F(384000000, P_DDRPLLAPSS, 1, 0, 0),
+ F(413000000, P_DDRPLLAPSS, 1, 0, 0),
+ F(448000000, P_DDRPLLAPSS, 1, 0, 0),
+ F(488000000, P_DDRPLLAPSS, 1, 0, 0),
F(500000000, P_FEPLL500, 1, 0, 0),
- F(626000000, P_DDRPLLAPSS, 1, 0, 0),
+ F(512000000, P_DDRPLLAPSS, 1, 0, 0),
+ F(537000000, P_DDRPLLAPSS, 1, 0, 0),
+ F(565000000, P_DDRPLLAPSS, 1, 0, 0),
+ F(597000000, P_DDRPLLAPSS, 1, 0, 0),
+ F(632000000, P_DDRPLLAPSS, 1, 0, 0),
+ F(672000000, P_DDRPLLAPSS, 1, 0, 0),
+ F(716000000, P_DDRPLLAPSS, 1, 0, 0),
{ }
};
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