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| author | Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> | 2016-06-17 13:25:14 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-06-21 09:21:06 +0200 |
| commit | 7d6cc0cddbc2f1953b2ff6f5930a065e40b94507 (patch) | |
| tree | b2d1f4299fe07f90576133492228dbeed49a68b5 | |
| parent | f7bb887fb898307dd575179303b710d933f242ea (diff) | |
| download | op-kernel-dev-7d6cc0cddbc2f1953b2ff6f5930a065e40b94507.zip op-kernel-dev-7d6cc0cddbc2f1953b2ff6f5930a065e40b94507.tar.gz | |
clk: renesas: r8a7795: Add DRIF clock
This patch adds DRIF module clocks for r8a7795 SoC.
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/r8a7795-cpg-mssr.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index ad01b0b..b9485ab 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -138,6 +138,14 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4), DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4), + DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), + DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), + DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), + DEF_MOD("drif4", 511, R8A7795_CLK_S3D2), + DEF_MOD("drif3", 512, R8A7795_CLK_S3D2), + DEF_MOD("drif2", 513, R8A7795_CLK_S3D2), + DEF_MOD("drif1", 514, R8A7795_CLK_S3D2), + DEF_MOD("drif0", 515, R8A7795_CLK_S3D2), DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), |
