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| author | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2018-03-22 16:33:17 +0000 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2018-03-23 11:16:21 +0000 |
| commit | 745029187a5465972fa2daf0fa43f1d2edb48de9 (patch) | |
| tree | 5dedc70202aa73093ea1a30a9207f73a31783ebe | |
| parent | 7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff) | |
| download | op-kernel-dev-745029187a5465972fa2daf0fa43f1d2edb48de9.zip op-kernel-dev-745029187a5465972fa2daf0fa43f1d2edb48de9.tar.gz | |
PCI: pcie-xilinx-nwl: Fix mask value to disable MSIs
Compiling the xilinx-nwl driver with sparse checks result in the
following warning:
drivers/pci/host/pcie-xilinx-nwl.c:633:38: sparse: cast truncates bits
from constant value (ffffffff00000000 becomes 0)
Fix it by explicitly writing 0 to mask interrupts instead of relying
on a bogus cast applied to the mask bitwise complement.
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
| -rw-r--r-- | drivers/pci/host/pcie-xilinx-nwl.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c index 0acaf48..4839ae5 100644 --- a/drivers/pci/host/pcie-xilinx-nwl.c +++ b/drivers/pci/host/pcie-xilinx-nwl.c @@ -630,7 +630,7 @@ static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) * For high range MSI interrupts: disable, clear any pending, * and enable */ - nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); + nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI); @@ -641,7 +641,7 @@ static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) * For low range MSI interrupts: disable, clear any pending, * and enable */ - nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); + nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO); |
