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| author | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2007-12-24 19:46:06 -0600 |
|---|---|---|
| committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2007-12-24 19:46:06 -0600 |
| commit | 67196d7275fcbc62c41c34400855d3d3c95d8d1d (patch) | |
| tree | 2657066718f7a9e5d3c24a7fed1940e0c600dcad | |
| parent | 3f8c5c3b4d07fa24e7081a54798ddfab7360a102 (diff) | |
| download | op-kernel-dev-67196d7275fcbc62c41c34400855d3d3c95d8d1d.zip op-kernel-dev-67196d7275fcbc62c41c34400855d3d3c95d8d1d.tar.gz | |
[POWERPC] 4xx: Minor coding style cleanups for 4xx bootwrapper
Remove some unneeded braces and make a busy loop more obvious.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
| -rw-r--r-- | arch/powerpc/boot/4xx.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index 1a83efe..33f25b6 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c @@ -243,7 +243,8 @@ void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1) *emac1 = EMAC_RESET; mtdcr(DCRN_MAL0_CFG, MAL_RESET); - while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) {}; + while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) + ; /* loop until reset takes effect */ } /* Read 4xx EBC bus bridge registers to get mappings of the peripheral @@ -515,19 +516,17 @@ void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk) opb = plb / opdv; ebc = plb / epdv; - if (cpc0_cr0 & 0x80) { + if (cpc0_cr0 & 0x80) /* uart0 uses the external clock */ uart0 = ser_clk; - } else { + else uart0 = cpu / udiv; - } - if (cpc0_cr0 & 0x40) { + if (cpc0_cr0 & 0x40) /* uart1 uses the external clock */ uart1 = ser_clk; - } else { + else uart1 = cpu / udiv; - } /* setup the timebase clock to tick at the cpu frequency */ cpc0_cr1 = cpc0_cr1 & ~0x00800000; |
