diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2012-05-14 17:31:45 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-05-14 17:31:45 +0200 |
| commit | 66a2886d867343eff6bf2646bea2c923d0cbf620 (patch) | |
| tree | ad44dcca4fa410ab2c16b4964f6c19571421b4df | |
| parent | d2819f80d465672b09c2f4cb52303b7f951c4d0f (diff) | |
| parent | f613e220aebfafb653f7ce264950c15c99e27f2a (diff) | |
| download | op-kernel-dev-66a2886d867343eff6bf2646bea2c923d0cbf620.zip op-kernel-dev-66a2886d867343eff6bf2646bea2c923d0cbf620.tar.gz | |
Merge branch 'spear/dt' into spear/clock
Conflicts:
arch/arm/mach-spear3xx/clock.c
arch/arm/mach-spear3xx/include/mach/generic.h
arch/arm/mach-spear3xx/include/mach/misc_regs.h
arch/arm/mach-spear3xx/spear320.c
arch/arm/mach-spear6xx/clock.c
arch/arm/mach-spear6xx/include/mach/misc_regs.h
Resolve even more merge conflicts.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
35 files changed, 462 insertions, 721 deletions
diff --git a/Documentation/devicetree/bindings/arm/spear-timer.txt b/Documentation/devicetree/bindings/arm/spear-timer.txt new file mode 100644 index 0000000..c001722 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/spear-timer.txt @@ -0,0 +1,18 @@ +* SPEAr ARM Timer + +** Timer node required properties: + +- compatible : Should be: + "st,spear-timer" +- reg: Address range of the timer registers +- interrupt-parent: Should be the phandle for the interrupt controller + that services interrupts for this device +- interrupt: Should contain the timer interrupt number + +Example: + + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <2>; + }; diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts index 402ca0d..fc82b1a 100644 --- a/arch/arm/boot/dts/spear300-evb.dts +++ b/arch/arm/boot/dts/spear300-evb.dts @@ -87,6 +87,31 @@ smi: flash@fc000000 { status = "okay"; + clock-rate=<50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; }; spi0: spi@d0100000 { @@ -119,87 +144,87 @@ }; kbd@a0000000 { - linux,keymap = < 0x00010000 - 0x00020100 - 0x00030200 - 0x00040300 - 0x00050400 - 0x00060500 - 0x00070600 - 0x00080700 - 0x00090800 - 0x000a0001 - 0x000c0101 - 0x000d0201 - 0x000e0301 - 0x000f0401 - 0x00100501 - 0x00110601 - 0x00120701 - 0x00130801 - 0x00140002 - 0x00150102 - 0x00160202 - 0x00170302 - 0x00180402 - 0x00190502 - 0x001a0602 - 0x001b0702 - 0x001c0802 - 0x001d0003 - 0x001e0103 - 0x001f0203 - 0x00200303 - 0x00210403 - 0x00220503 - 0x00230603 - 0x00240703 - 0x00250803 - 0x00260004 - 0x00270104 - 0x00280204 - 0x00290304 - 0x002a0404 - 0x002b0504 - 0x002c0604 - 0x002d0704 - 0x002e0804 - 0x002f0005 - 0x00300105 - 0x00310205 - 0x00320305 - 0x00330405 - 0x00340505 - 0x00350605 - 0x00360705 - 0x00370805 - 0x00380006 - 0x00390106 - 0x003a0206 - 0x003b0306 - 0x003c0406 - 0x003d0506 - 0x003e0606 - 0x003f0706 - 0x00400806 - 0x00410007 - 0x00420107 - 0x00430207 - 0x00440307 - 0x00450407 - 0x00460507 - 0x00470607 - 0x00480707 - 0x00490807 - 0x004a0008 - 0x004b0108 - 0x004c0208 - 0x004d0308 - 0x004e0408 - 0x004f0508 - 0x00500608 - 0x00510708 - 0x00520808 >; + linux,keymap = < 0x00000001 + 0x00010002 + 0x00020003 + 0x00030004 + 0x00040005 + 0x00050006 + 0x00060007 + 0x00070008 + 0x00080009 + 0x0100000a + 0x0101000c + 0x0102000d + 0x0103000e + 0x0104000f + 0x01050010 + 0x01060011 + 0x01070012 + 0x01080013 + 0x02000014 + 0x02010015 + 0x02020016 + 0x02030017 + 0x02040018 + 0x02050019 + 0x0206001a + 0x0207001b + 0x0208001c + 0x0300001d + 0x0301001e + 0x0302001f + 0x03030020 + 0x03040021 + 0x03050022 + 0x03060023 + 0x03070024 + 0x03080025 + 0x04000026 + 0x04010027 + 0x04020028 + 0x04030029 + 0x0404002a + 0x0405002b + 0x0406002c + 0x0407002d + 0x0408002e + 0x0500002f + 0x05010030 + 0x05020031 + 0x05030032 + 0x05040033 + 0x05050034 + 0x05060035 + 0x05070036 + 0x05080037 + 0x06000038 + 0x06010039 + 0x0602003a + 0x0603003b + 0x0604003c + 0x0605003d + 0x0606003e + 0x0607003f + 0x06080040 + 0x07000041 + 0x07010042 + 0x07020043 + 0x07030044 + 0x07040045 + 0x07050046 + 0x07060047 + 0x07070048 + 0x07080049 + 0x0800004a + 0x0801004b + 0x0802004c + 0x0803004d + 0x0804004e + 0x0805004f + 0x08060050 + 0x08070051 + 0x08080052 >; autorepeat; st,mode = <0>; status = "okay"; diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts index 6d95317..dc5e2d4 100644 --- a/arch/arm/boot/dts/spear310-evb.dts +++ b/arch/arm/boot/dts/spear310-evb.dts @@ -103,11 +103,27 @@ clock-rate=<50000000>; flash@f8000000 { - label = "m25p64"; - reg = <0xf8000000 0x800000>; #address-cells = <1>; #size-cells = <1>; + reg = <0xf8000000 0x800000>; st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; }; }; diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts index 0c6463b..6308fa3 100644 --- a/arch/arm/boot/dts/spear320-evb.dts +++ b/arch/arm/boot/dts/spear320-evb.dts @@ -110,6 +110,31 @@ smi: flash@fc000000 { status = "okay"; + clock-rate=<50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; }; spi0: spi@d0100000 { diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi index 0ae7c8e..91072553 100644 --- a/arch/arm/boot/dts/spear3xx.dtsi +++ b/arch/arm/boot/dts/spear3xx.dtsi @@ -139,6 +139,12 @@ interrupts = <12>; status = "disabled"; }; + + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <2>; + }; }; }; }; diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts index 790a7a8..1119c22 100644 --- a/arch/arm/boot/dts/spear600-evb.dts +++ b/arch/arm/boot/dts/spear600-evb.dts @@ -33,6 +33,35 @@ status = "okay"; }; + smi: flash@fc000000 { + status = "okay"; + clock-rate=<50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; + }; + apb { serial@d0000000 { status = "okay"; diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi index d777e3a..089f0a4 100644 --- a/arch/arm/boot/dts/spear600.dtsi +++ b/arch/arm/boot/dts/spear600.dtsi @@ -177,6 +177,12 @@ interrupts = <28>; status = "disabled"; }; + + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <16>; + }; }; }; }; diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig index 7ed4291..865980c 100644 --- a/arch/arm/configs/spear3xx_defconfig +++ b/arch/arm/configs/spear3xx_defconfig @@ -14,6 +14,9 @@ CONFIG_BINFMT_MISC=y CONFIG_NET=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y @@ -73,6 +76,7 @@ CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig index cf94bc7..a2a1265 100644 --- a/arch/arm/configs/spear6xx_defconfig +++ b/arch/arm/configs/spear6xx_defconfig @@ -8,11 +8,13 @@ CONFIG_MODVERSIONS=y CONFIG_PARTITION_ADVANCED=y CONFIG_PLAT_SPEAR=y CONFIG_ARCH_SPEAR6XX=y -CONFIG_BOARD_SPEAR600_DT=y CONFIG_BINFMT_MISC=y CONFIG_NET=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y @@ -64,6 +66,7 @@ CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h index c10eac6..4a95b94 100644 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/arch/arm/mach-spear3xx/include/mach/generic.h @@ -21,22 +21,13 @@ #include <asm/mach/time.h> #include <asm/mach/map.h> -/* spear3xx declarations */ -/* - * Each GPT has 2 timer channels - * Following GPT channels will be used as clock source and clockevent - */ -#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE -#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1 -#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2 - /* Add spear3xx family device structure declarations here */ extern struct sys_timer spear3xx_timer; extern struct pl022_ssp_controller pl022_plat_data; extern struct pl08x_platform_data pl080_plat_data; /* Add spear3xx family function declarations here */ -void __init spear_setup_timer(void); +void __init spear_setup_of_timer(void); void __init spear3xx_clk_init(void); void __init spear3xx_map_io(void); void __init spear3xx_dt_init_irq(void); diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h index defa374..40a8c17 100644 --- a/arch/arm/mach-spear3xx/include/mach/hardware.h +++ b/arch/arm/mach-spear3xx/include/mach/hardware.h @@ -1,20 +1 @@ -/* - * arch/arm/mach-spear3xx/include/mach/hardware.h - * - * Hardware definitions for SPEAr3xx machine family - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_HARDWARE_H -#define __MACH_HARDWARE_H - -#include <plat/hardware.h> -#include <mach/spear.h> - -#endif /* __MACH_HARDWARE_H */ +/* empty */ diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h index 6e26544..51bd62a 100644 --- a/arch/arm/mach-spear3xx/include/mach/irqs.h +++ b/arch/arm/mach-spear3xx/include/mach/irqs.h @@ -14,141 +14,14 @@ #ifndef __MACH_IRQS_H #define __MACH_IRQS_H -/* SPEAr3xx IRQ definitions */ -#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0 +/* FIXME: probe all these from DT */ #define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1 -#define SPEAR3XX_IRQ_CPU_GPT1_1 2 -#define SPEAR3XX_IRQ_CPU_GPT1_2 3 -#define SPEAR3XX_IRQ_BASIC_GPT1_1 4 -#define SPEAR3XX_IRQ_BASIC_GPT1_2 5 -#define SPEAR3XX_IRQ_BASIC_GPT2_1 6 -#define SPEAR3XX_IRQ_BASIC_GPT2_2 7 -#define SPEAR3XX_IRQ_BASIC_DMA 8 -#define SPEAR3XX_IRQ_BASIC_SMI 9 -#define SPEAR3XX_IRQ_BASIC_RTC 10 -#define SPEAR3XX_IRQ_BASIC_GPIO 11 -#define SPEAR3XX_IRQ_BASIC_WDT 12 -#define SPEAR3XX_IRQ_DDR_CONTROLLER 13 -#define SPEAR3XX_IRQ_SYS_ERROR 14 -#define SPEAR3XX_IRQ_WAKEUP_RCV 15 -#define SPEAR3XX_IRQ_JPEG 16 -#define SPEAR3XX_IRQ_IRDA 17 -#define SPEAR3XX_IRQ_ADC 18 -#define SPEAR3XX_IRQ_UART 19 -#define SPEAR3XX_IRQ_SSP 20 -#define SPEAR3XX_IRQ_I2C 21 -#define SPEAR3XX_IRQ_MAC_1 22 -#define SPEAR3XX_IRQ_MAC_2 23 -#define SPEAR3XX_IRQ_USB_DEV 24 -#define SPEAR3XX_IRQ_USB_H_OHCI_0 25 -#define SPEAR3XX_IRQ_USB_H_EHCI_0 26 -#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0 -#define SPEAR3XX_IRQ_USB_H_OHCI_1 27 #define SPEAR3XX_IRQ_GEN_RAS_1 28 #define SPEAR3XX_IRQ_GEN_RAS_2 29 #define SPEAR3XX_IRQ_GEN_RAS_3 30 -#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31 #define SPEAR3XX_IRQ_VIC_END 32 - #define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END -/* SPEAr300 Virtual irq definitions */ -/* IRQs sharing IRQ_GEN_RAS_1 */ -#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0) -#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1) -#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2) -#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3) -#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4) -#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5) -#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6) -#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7) -#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8) - -/* IRQs sharing IRQ_GEN_RAS_3 */ -#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3 - -/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM - -/* SPEAr310 Virtual irq definitions */ -/* IRQs sharing IRQ_GEN_RAS_1 */ -#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0) -#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1) -#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2) -#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3) -#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4) -#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5) -#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6) -#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7) - -/* IRQs sharing IRQ_GEN_RAS_2 */ -#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) -#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) -#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10) -#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11) -#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12) - -/* IRQs sharing IRQ_GEN_RAS_3 */ -#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13) -#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14) - -/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15) -#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16) -#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) - -/* SPEAr320 Virtual irq definitions */ -/* IRQs sharing IRQ_GEN_RAS_1 */ -#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0) -#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1) -#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2) - -/* IRQs sharing IRQ_GEN_RAS_2 */ -#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2 - -/* IRQs sharing IRQ_GEN_RAS_3 */ -#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3) -#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4) -#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5) - -/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6) -#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7) -#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) -#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) -#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10) -#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11) -#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12) -#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13) -#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14) -#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) -#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) - -/* - * GPIO pins virtual irqs - * Use the lowest number for the GPIO virtual IRQs base on which subarchs - * we have compiled in - */ -#if defined(CONFIG_MACH_SPEAR310) -#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18) -#elif defined(CONFIG_MACH_SPEAR320) -#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17) -#else -#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9) -#endif - -#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8) -#define SPEAR3XX_PLGPIO_COUNT 102 - -#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) -#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8) -#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \ - SPEAR3XX_PLGPIO_COUNT) -#else -#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8) -#endif - -#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END -#define NR_IRQS SPEAR3XX_VIRQ_END +#define NR_IRQS 160 #endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h index 50cfe0d..18e2ac5 100644 --- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h @@ -14,9 +14,9 @@ #ifndef __MACH_MISC_REGS_H #define __MACH_MISC_REGS_H -#include <mach/hardware.h> #include <mach/spear.h> #define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) +#define DMA_CHN_CFG (MISC_BASE + 0x0A0) #endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h index e7bc8ba..51eb953 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear.h +++ b/arch/arm/mach-spear3xx/include/mach/spear.h @@ -15,61 +15,26 @@ #define __MACH_SPEAR3XX_H #include <asm/memory.h> -#include <mach/spear300.h> -#include <mach/spear310.h> -#include <mach/spear320.h> - -#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000) - -#define SPEAR3XX_ICM9_BASE UL(0xC0000000) /* ICM1 - Low speed connection */ #define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) #define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000) #define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) #define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE) -#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000) #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) -#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000) -#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000) -#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000) -#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000) - -/* ICM2 - Application Subsystem */ -#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000) -#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000) - -/* ICM4 - High Speed Connection */ -#define SPEAR3XX_ICM4_BASE UL(0xE0000000) -#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000) -#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000) -#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000) -#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000) -#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000) -#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000) -#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000) -#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000) /* ML1 - Multi Layer CPU Subsystem */ #define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) -#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) -#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) +#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) /* ICM3 - Basic Subsystem */ -#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000) #define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) #define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) #define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) -#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) -#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000) -#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000) -#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000) -#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000) #define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE) #define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) #define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE) -#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000) /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h deleted file mode 100644 index 3b6ea07..0000000 --- a/arch/arm/mach-spear3xx/include/mach/spear300.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/spear300.h - * - * SPEAr300 Machine specific definition - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifdef CONFIG_MACH_SPEAR300 - -#ifndef __MACH_SPEAR300_H -#define __MACH_SPEAR300_H - -/* Base address of various IPs */ -#define SPEAR300_TELECOM_BASE UL(0x50000000) - -/* Interrupt registers offsets and masks */ -#define SPEAR300_INT_ENB_MASK_REG 0x54 -#define SPEAR300_INT_STS_MASK_REG 0x58 -#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0) -#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1) -#define SPEAR300_I2S_IRQ_MASK (1 << 2) -#define SPEAR300_TDM_IRQ_MASK (1 << 3) -#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4) -#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5) -#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6) -#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7) -#define SPEAR300_GPIO1_IRQ_MASK (1 << 8) - -#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF - -#define SPEAR300_CLCD_BASE UL(0x60000000) -#define SPEAR300_SDHCI_BASE UL(0x70000000) -#define SPEAR300_NAND_0_BASE UL(0x80000000) -#define SPEAR300_NAND_1_BASE UL(0x84000000) -#define SPEAR300_NAND_2_BASE UL(0x88000000) -#define SPEAR300_NAND_3_BASE UL(0x8c000000) -#define SPEAR300_NOR_0_BASE UL(0x90000000) -#define SPEAR300_NOR_1_BASE UL(0x91000000) -#define SPEAR300_NOR_2_BASE UL(0x92000000) -#define SPEAR300_NOR_3_BASE UL(0x93000000) -#define SPEAR300_FSMC_BASE UL(0x94000000) -#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000) -#define SPEAR300_KEYBOARD_BASE UL(0xA0000000) -#define SPEAR300_GPIO_BASE UL(0xA9000000) - -#endif /* __MACH_SPEAR300_H */ - -#endif /* CONFIG_MACH_SPEAR300 */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h deleted file mode 100644 index 1567d0da..0000000 --- a/arch/arm/mach-spear3xx/include/mach/spear310.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/spear310.h - * - * SPEAr310 Machine specific definition - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifdef CONFIG_MACH_SPEAR310 - -#ifndef __MACH_SPEAR310_H -#define __MACH_SPEAR310_H - -#define SPEAR310_NAND_BASE UL(0x40000000) -#define SPEAR310_FSMC_BASE UL(0x44000000) -#define SPEAR310_UART1_BASE UL(0xB2000000) -#define SPEAR310_UART2_BASE UL(0xB2080000) -#define SPEAR310_UART3_BASE UL(0xB2100000) -#define SPEAR310_UART4_BASE UL(0xB2180000) -#define SPEAR310_UART5_BASE UL(0xB2200000) -#define SPEAR310_HDLC_BASE UL(0xB2800000) -#define SPEAR310_RS485_0_BASE UL(0xB3000000) -#define SPEAR310_RS485_1_BASE UL(0xB3800000) -#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) - -/* Interrupt registers offsets and masks */ -#define SPEAR310_INT_STS_MASK_REG 0x04 -#define SPEAR310_SMII0_IRQ_MASK (1 << 0) -#define SPEAR310_SMII1_IRQ_MASK (1 << 1) -#define SPEAR310_SMII2_IRQ_MASK (1 << 2) -#define SPEAR310_SMII3_IRQ_MASK (1 << 3) -#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) -#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) -#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) -#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) -#define SPEAR310_UART1_IRQ_MASK (1 << 8) -#define SPEAR310_UART2_IRQ_MASK (1 << 9) -#define SPEAR310_UART3_IRQ_MASK (1 << 10) -#define SPEAR310_UART4_IRQ_MASK (1 << 11) -#define SPEAR310_UART5_IRQ_MASK (1 << 12) -#define SPEAR310_EMI_IRQ_MASK (1 << 13) -#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) -#define SPEAR310_RS485_0_IRQ_MASK (1 << 15) -#define SPEAR310_RS485_1_IRQ_MASK (1 << 16) - -#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF -#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 -#define SPEAR310_SHIRQ_RAS3_MASK 0x02000 -#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 - -#endif /* __MACH_SPEAR310_H */ - -#endif /* CONFIG_MACH_SPEAR310 */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h deleted file mode 100644 index 8cfa83f..0000000 --- a/arch/arm/mach-spear3xx/include/mach/spear320.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/spear320.h - * - * SPEAr320 Machine specific definition - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifdef CONFIG_MACH_SPEAR320 - -#ifndef __MACH_SPEAR320_H -#define __MACH_SPEAR320_H - -#define SPEAR320_EMI_CTRL_BASE UL(0x40000000) -#define SPEAR320_FSMC_BASE UL(0x4C000000) -#define SPEAR320_NAND_BASE UL(0x50000000) -#define SPEAR320_I2S_BASE UL(0x60000000) -#define SPEAR320_SDHCI_BASE UL(0x70000000) -#define SPEAR320_CLCD_BASE UL(0x90000000) -#define SPEAR320_PAR_PORT_BASE UL(0xA0000000) -#define SPEAR320_CAN0_BASE UL(0xA1000000) -#define SPEAR320_CAN1_BASE UL(0xA2000000) -#define SPEAR320_UART1_BASE UL(0xA3000000) -#define SPEAR320_UART2_BASE UL(0xA4000000) -#define SPEAR320_SSP0_BASE UL(0xA5000000) -#define SPEAR320_SSP1_BASE UL(0xA6000000) -#define SPEAR320_I2C_BASE UL(0xA7000000) -#define SPEAR320_PWM_BASE UL(0xA8000000) -#define SPEAR320_SMII0_BASE UL(0xAA000000) -#define SPEAR320_SMII1_BASE UL(0xAB000000) -#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) - -/* Interrupt registers offsets and masks */ -#define SPEAR320_INT_STS_MASK_REG 0x04 -#define SPEAR320_INT_CLR_MASK_REG 0x04 -#define SPEAR320_INT_ENB_MASK_REG 0x08 -#define SPEAR320_GPIO_IRQ_MASK (1 << 0) -#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1) -#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2) -#define SPEAR320_EMI_IRQ_MASK (1 << 7) -#define SPEAR320_CLCD_IRQ_MASK (1 << 8) -#define SPEAR320_SPP_IRQ_MASK (1 << 9) -#define SPEAR320_SDHCI_IRQ_MASK (1 << 10) -#define SPEAR320_CAN_U_IRQ_MASK (1 << 11) -#define SPEAR320_CAN_L_IRQ_MASK (1 << 12) -#define SPEAR320_UART1_IRQ_MASK (1 << 13) -#define SPEAR320_UART2_IRQ_MASK (1 << 14) -#define SPEAR320_SSP1_IRQ_MASK (1 << 15) -#define SPEAR320_SSP2_IRQ_MASK (1 << 16) -#define SPEAR320_SMII0_IRQ_MASK (1 << 17) -#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18) -#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19) -#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) -#define SPEAR320_I2C1_IRQ_MASK (1 << 21) - -#define SPEAR320_SHIRQ_RAS1_MASK 0x000380 -#define SPEAR320_SHIRQ_RAS3_MASK 0x000007 -#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 - -#endif /* __MACH_SPEAR320_H */ - -#endif /* CONFIG_MACH_SPEAR320 */ diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c index 2db0bd1..f74a05b 100644 --- a/arch/arm/mach-spear3xx/spear300.c +++ b/arch/arm/mach-spear3xx/spear300.c @@ -19,7 +19,46 @@ #include <asm/mach/arch.h> #include <plat/shirq.h> #include <mach/generic.h> -#include <mach/hardware.h> +#include <mach/spear.h> + +/* Base address of various IPs */ +#define SPEAR300_TELECOM_BASE UL(0x50000000) + +/* Interrupt registers offsets and masks */ +#define SPEAR300_INT_ENB_MASK_REG 0x54 +#define SPEAR300_INT_STS_MASK_REG 0x58 +#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0) +#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1) +#define SPEAR300_I2S_IRQ_MASK (1 << 2) +#define SPEAR300_TDM_IRQ_MASK (1 << 3) +#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4) +#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5) +#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6) +#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7) +#define SPEAR300_GPIO1_IRQ_MASK (1 << 8) + +#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF + +#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000) + + +/* SPEAr300 Virtual irq definitions */ +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0) +#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1) +#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2) +#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3) +#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4) +#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5) +#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6) +#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7) +#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8) + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3 + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM /* spear3xx shared irq */ static struct shirq_dev_config shirq_ras1_config[] = { @@ -298,7 +337,6 @@ static const char * const spear300_dt_board_compat[] = { static void __init spear300_map_io(void) { spear3xx_map_io(); - spear300_clk_init(); } DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c index aec07c9..84dfb09 100644 --- a/arch/arm/mach-spear3xx/spear310.c +++ b/arch/arm/mach-spear3xx/spear310.c @@ -20,7 +20,67 @@ #include <asm/mach/arch.h> #include <plat/shirq.h> #include <mach/generic.h> -#include <mach/hardware.h> +#include <mach/spear.h> + +#define SPEAR310_UART1_BASE UL(0xB2000000) +#define SPEAR310_UART2_BASE UL(0xB2080000) +#define SPEAR310_UART3_BASE UL(0xB2100000) +#define SPEAR310_UART4_BASE UL(0xB2180000) +#define SPEAR310_UART5_BASE UL(0xB2200000) +#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) + +/* Interrupt registers offsets and masks */ +#define SPEAR310_INT_STS_MASK_REG 0x04 +#define SPEAR310_SMII0_IRQ_MASK (1 << 0) +#define SPEAR310_SMII1_IRQ_MASK (1 << 1) +#define SPEAR310_SMII2_IRQ_MASK (1 << 2) +#define SPEAR310_SMII3_IRQ_MASK (1 << 3) +#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) +#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) +#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) +#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) +#define SPEAR310_UART1_IRQ_MASK (1 << 8) +#define SPEAR310_UART2_IRQ_MASK (1 << 9) +#define SPEAR310_UART3_IRQ_MASK (1 << 10) +#define SPEAR310_UART4_IRQ_MASK (1 << 11) +#define SPEAR310_UART5_IRQ_MASK (1 << 12) +#define SPEAR310_EMI_IRQ_MASK (1 << 13) +#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) +#define SPEAR310_RS485_0_IRQ_MASK (1 << 15) +#define SPEAR310_RS485_1_IRQ_MASK (1 << 16) + +#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF +#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 +#define SPEAR310_SHIRQ_RAS3_MASK 0x02000 +#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 + +/* SPEAr310 Virtual irq definitions */ +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0) +#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1) +#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2) +#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3) +#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4) +#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5) +#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6) +#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7) + +/* IRQs sharing IRQ_GEN_RAS_2 */ +#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) +#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) +#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10) +#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11) +#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12) + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13) +#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14) + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15) +#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16) +#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) + /* spear3xx shared irq */ static struct shirq_dev_config shirq_ras1_config[] = { @@ -418,7 +478,6 @@ static const char * const spear310_dt_board_compat[] = { static void __init spear310_map_io(void) { spear3xx_map_io(); - spear310_clk_init(); } DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c index fb28c18..a88fa84 100644 --- a/arch/arm/mach-spear3xx/spear320.c +++ b/arch/arm/mach-spear3xx/spear320.c @@ -21,9 +21,67 @@ #include <asm/mach/arch.h> #include <plat/shirq.h> #include <mach/generic.h> -#include <mach/hardware.h> #include <mach/spear.h> +#define SPEAR320_UART1_BASE UL(0xA3000000) +#define SPEAR320_UART2_BASE UL(0xA4000000) +#define SPEAR320_SSP0_BASE UL(0xA5000000) +#define SPEAR320_SSP1_BASE UL(0xA6000000) + +/* Interrupt registers offsets and masks */ +#define SPEAR320_INT_STS_MASK_REG 0x04 +#define SPEAR320_INT_CLR_MASK_REG 0x04 +#define SPEAR320_INT_ENB_MASK_REG 0x08 +#define SPEAR320_GPIO_IRQ_MASK (1 << 0) +#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1) +#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2) +#define SPEAR320_EMI_IRQ_MASK (1 << 7) +#define SPEAR320_CLCD_IRQ_MASK (1 << 8) +#define SPEAR320_SPP_IRQ_MASK (1 << 9) +#define SPEAR320_SDHCI_IRQ_MASK (1 << 10) +#define SPEAR320_CAN_U_IRQ_MASK (1 << 11) +#define SPEAR320_CAN_L_IRQ_MASK (1 << 12) +#define SPEAR320_UART1_IRQ_MASK (1 << 13) +#define SPEAR320_UART2_IRQ_MASK (1 << 14) +#define SPEAR320_SSP1_IRQ_MASK (1 << 15) +#define SPEAR320_SSP2_IRQ_MASK (1 << 16) +#define SPEAR320_SMII0_IRQ_MASK (1 << 17) +#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18) +#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19) +#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) +#define SPEAR320_I2C1_IRQ_MASK (1 << 21) + +#define SPEAR320_SHIRQ_RAS1_MASK 0x000380 +#define SPEAR320_SHIRQ_RAS3_MASK 0x000007 +#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 + +/* SPEAr320 Virtual irq definitions */ +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0) +#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1) +#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2) + +/* IRQs sharing IRQ_GEN_RAS_2 */ +#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2 + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3) +#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4) +#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5) + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6) +#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7) +#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) +#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) +#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10) +#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11) +#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12) +#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13) +#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14) +#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) +#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) + /* spear3xx shared irq */ static struct shirq_dev_config shirq_ras1_config[] = { { @@ -422,10 +480,19 @@ static const char * const spear320_dt_board_compat[] = { NULL, }; +struct map_desc spear320_io_desc[] __initdata = { + { + .virtual = VA_SPEAR320_SOC_CONFIG_BASE, + .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, +}; + static void __init spear320_map_io(void) { + iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc)); spear3xx_map_io(); - spear320_clk_init(); } DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index 71927c7..f22419e 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -21,7 +21,7 @@ #include <asm/hardware/vic.h> #include <plat/pl080.h> #include <mach/generic.h> -#include <mach/hardware.h> +#include <mach/spear.h> /* ssp device registration */ struct pl022_ssp_controller pl022_plat_data = { @@ -111,7 +111,7 @@ static void __init spear3xx_timer_init(void) clk_put(gpt_clk); clk_put(pclk); - spear_setup_timer(); + spear_setup_of_timer(); } struct sys_timer spear3xx_timer = { diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h index 116b993..65514b15 100644 --- a/arch/arm/mach-spear6xx/include/mach/generic.h +++ b/arch/arm/mach-spear6xx/include/mach/generic.h @@ -15,34 +15,9 @@ #define __MACH_GENERIC_H #include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/amba/bus.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -/* - * Each GPT has 2 timer channels - * Following GPT channels will be used as clock source and clockevent - */ -#define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE -#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1 -#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2 - -/* Add spear6xx family device structure declarations here */ -extern struct amba_device gpio_device[]; -extern struct amba_device uart_device[]; -extern struct sys_timer spear6xx_timer; - -/* Add spear6xx family function declarations here */ -void __init spear_setup_timer(void); -void __init spear6xx_map_io(void); -void __init spear6xx_init_irq(void); -void __init spear6xx_init(void); -void __init spear600_init(void); -void __init spear6xx_clk_init(void); +void __init spear_setup_of_timer(void); void spear_restart(char, const char *); - -/* Add spear600 machine device structure declarations here */ +void __init spear6xx_clk_init(void); #endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h index 0b3f96a..40a8c17 100644 --- a/arch/arm/mach-spear6xx/include/mach/hardware.h +++ b/arch/arm/mach-spear6xx/include/mach/hardware.h @@ -1,23 +1 @@ -/* - * arch/arm/mach-spear6xx/include/mach/hardware.h - * - * Hardware definitions for SPEAr6xx machine family - * - * Copyright (C) 2009 ST Microelectronics - * Rajeev Kumar<rajeev-dlh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_HARDWARE_H -#define __MACH_HARDWARE_H - -#include <plat/hardware.h> -#include <mach/spear.h> - -/* Vitual to physical translation of statically mapped space */ -#define IO_ADDRESS(x) (x | 0xF0000000) - -#endif /* __MACH_HARDWARE_H */ +/* empty */ diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h index 8f214b0..37a5c41 100644 --- a/arch/arm/mach-spear6xx/include/mach/irqs.h +++ b/arch/arm/mach-spear6xx/include/mach/irqs.h @@ -16,82 +16,10 @@ /* IRQ definitions */ /* VIC 1 */ -#define IRQ_INTRCOMM_SW_IRQ 0 -#define IRQ_INTRCOMM_CPU_1 1 -#define IRQ_INTRCOMM_CPU_2 2 -#define IRQ_INTRCOMM_RAS2A11_1 3 -#define IRQ_INTRCOMM_RAS2A11_2 4 -#define IRQ_INTRCOMM_RAS2A12_1 5 -#define IRQ_INTRCOMM_RAS2A12_2 6 -#define IRQ_GEN_RAS_0 7 -#define IRQ_GEN_RAS_1 8 -#define IRQ_GEN_RAS_2 9 -#define IRQ_GEN_RAS_3 10 -#define IRQ_GEN_RAS_4 11 -#define IRQ_GEN_RAS_5 12 -#define IRQ_GEN_RAS_6 13 -#define IRQ_GEN_RAS_7 14 -#define IRQ_GEN_RAS_8 15 -#define IRQ_CPU_GPT1_1 16 -#define IRQ_CPU_GPT1_2 17 -#define IRQ_LOCAL_GPIO 18 -#define IRQ_PLL_UNLOCK 19 -#define IRQ_JPEG 20 -#define IRQ_FSMC 21 -#define IRQ_IRDA 22 -#define IRQ_RESERVED 23 -#define IRQ_UART_0 24 -#define IRQ_UART_1 25 -#define IRQ_SSP_1 26 -#define IRQ_SSP_2 27 -#define IRQ_I2C 28 -#define IRQ_GEN_RAS_9 29 -#define IRQ_GEN_RAS_10 30 -#define IRQ_GEN_RAS_11 31 - -/* VIC 2 */ -#define IRQ_APPL_GPT1_1 32 -#define IRQ_APPL_GPT1_2 33 -#define IRQ_APPL_GPT2_1 34 -#define IRQ_APPL_GPT2_2 35 -#define IRQ_APPL_GPIO 36 -#define IRQ_APPL_SSP 37 -#define IRQ_APPL_ADC 38 -#define IRQ_APPL_RESERVED 39 -#define IRQ_AHB_EXP_MASTER 40 -#define IRQ_DDR_CONTROLLER 41 -#define IRQ_BASIC_DMA 42 -#define IRQ_BASIC_RESERVED1 43 -#define IRQ_BASIC_SMI 44 -#define IRQ_BASIC_CLCD 45 -#define IRQ_EXP_AHB_1 46 -#define IRQ_EXP_AHB_2 47 -#define IRQ_BASIC_GPT1_1 48 -#define IRQ_BASIC_GPT1_2 49 -#define IRQ_BASIC_RTC 50 -#define IRQ_BASIC_GPIO 51 -#define IRQ_BASIC_WDT 52 -#define IRQ_BASIC_RESERVED 53 -#define IRQ_AHB_EXP_SLAVE 54 -#define IRQ_GMAC_1 55 -#define IRQ_GMAC_2 56 -#define IRQ_USB_DEV 57 -#define IRQ_USB_H_OHCI_0 58 -#define IRQ_USB_H_EHCI_0 59 -#define IRQ_USB_H_OHCI_1 60 -#define IRQ_USB_H_EHCI_1 61 -#define IRQ_EXP_AHB_3 62 -#define IRQ_EXP_AHB_4 63 - #define IRQ_VIC_END 64 /* GPIO pins virtual irqs */ -#define SPEAR_GPIO_INT_BASE IRQ_VIC_END -#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE -#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8) -#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8) -#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8) -#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END) -#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) +#define VIRTUAL_IRQS 24 +#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) #endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h index 633074f..179e457 100644 --- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h @@ -14,9 +14,9 @@ #ifndef __MACH_MISC_REGS_H #define __MACH_MISC_REGS_H -#include <mach/hardware.h> #include <mach/spear.h> #define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) +#define DMA_CHN_CFG (MISC_BASE + 0x0A0) #endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h index 7fd6215..cb8ed2f 100644 --- a/arch/arm/mach-spear6xx/include/mach/spear.h +++ b/arch/arm/mach-spear6xx/include/mach/spear.h @@ -15,69 +15,25 @@ #define __MACH_SPEAR6XX_H #include <asm/memory.h> -#include <mach/spear600.h> -#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000) /* ICM1 - Low speed connection */ #define SPEAR6XX_ICM1_BASE UL(0xD0000000) - +#define VA_SPEAR6XX_ICM1_BASE UL(0xFD000000) #define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000) -#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) - -#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000) -#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000) -#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000) -#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000) -#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000) -#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000) -#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000) -#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000) -#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000) - -/* ICM2 - Application Subsystem */ -#define SPEAR6XX_ICM2_BASE UL(0xD8000000) -#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000) -#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000) -#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000) -#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000) -#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000) +#define VA_SPEAR6XX_ICM1_UART0_BASE (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE) /* ML-1, 2 - Multi Layer CPU Subsystem */ #define SPEAR6XX_ML_CPU_BASE UL(0xF0000000) -#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000) -#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000) -#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000) -#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE) -#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000) -#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE) +#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) /* ICM3 - Basic Subsystem */ -#define SPEAR6XX_ICM3_BASE UL(0xF8000000) -#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000) #define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000) +#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) #define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000) -#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) -#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000) -#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000) -#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000) -#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000) #define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) -#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) +#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE) #define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000) -#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) - -/* ICM4 - High Speed Connection */ -#define SPEAR6XX_ICM4_BASE UL(0xE0000000) -#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000) -#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000) -#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000) -#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000) -#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000) -#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000) -#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000) -#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000) -#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000) +#define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE) /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h deleted file mode 100644 index c068cc5..0000000 --- a/arch/arm/mach-spear6xx/include/mach/spear600.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-spear66xx/include/mach/spear600.h - * - * SPEAr600 Machine specific definition - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifdef CONFIG_MACH_SPEAR600 - -#ifndef __MACH_SPEAR600_H -#define __MACH_SPEAR600_H - -#endif /* __MACH_SPEAR600_H */ - -#endif /* CONFIG_MACH_SPEAR600 */ diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index e9031ec6..2e2e359 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c @@ -14,6 +14,8 @@ */ #include <linux/amba/pl08x.h> +#include <linux/clk.h> +#include <linux/err.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> @@ -21,9 +23,11 @@ #include <asm/hardware/pl080.h> #include <asm/hardware/vic.h> #include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/mach/map.h> #include <plat/pl080.h> #include <mach/generic.h> -#include <mach/hardware.h> +#include <mach/spear.h> /* dmac device registration */ static struct pl08x_channel_data spear600_dma_info[] = { @@ -384,32 +388,29 @@ struct pl08x_platform_data pl080_plat_data = { .num_slave_channels = ARRAY_SIZE(spear600_dma_info), }; -/* Following will create static virtual/physical mappings */ -static struct map_desc spear6xx_io_desc[] __initdata = { +/* + * Following will create 16MB static virtual/physical mappings + * PHYSICAL VIRTUAL + * 0xF0000000 0xF0000000 + * 0xF1000000 0xF1000000 + * 0xD0000000 0xFD000000 + * 0xFC000000 0xFC000000 + */ +struct map_desc spear6xx_io_desc[] __initdata = { { - .virtual = VA_SPEAR6XX_ICM1_UART0_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { - .virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE), - .length = SZ_4K, + .virtual = VA_SPEAR6XX_ML_CPU_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE), + .length = 2 * SZ_16M, .type = MT_DEVICE - }, { - .virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { - .virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE), - .length = SZ_4K, + }, { + .virtual = VA_SPEAR6XX_ICM1_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE), + .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE), - .length = SZ_4K, + .virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE), + .length = SZ_16M, .type = MT_DEVICE }, }; @@ -446,7 +447,7 @@ static void __init spear6xx_timer_init(void) clk_put(gpt_clk); clk_put(pclk); - spear_setup_timer(); + spear_setup_of_timer(); } struct sys_timer spear6xx_timer = { diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S index 02b160a..ab3de72 100644 --- a/arch/arm/plat-spear/include/plat/debug-macro.S +++ b/arch/arm/plat-spear/include/plat/debug-macro.S @@ -12,7 +12,7 @@ */ #include <linux/amba/serial.h> -#include <mach/hardware.h> +#include <mach/spear.h> .macro addruart, rp, rv, tmp mov \rp, #SPEAR_DBG_UART_BASE @ Physical base diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h deleted file mode 100644 index 70187d7..0000000 --- a/arch/arm/plat-spear/include/plat/hardware.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/hardware.h - * - * Hardware definitions for SPEAr - * - * Copyright (C) 2010 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PLAT_HARDWARE_H -#define __PLAT_HARDWARE_H - -#endif /* __PLAT_HARDWARE_H */ diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h index 1bf8452..6dd455b 100644 --- a/arch/arm/plat-spear/include/plat/uncompress.h +++ b/arch/arm/plat-spear/include/plat/uncompress.h @@ -13,7 +13,7 @@ #include <linux/io.h> #include <linux/amba/serial.h> -#include <mach/hardware.h> +#include <mach/spear.h> #ifndef __PLAT_UNCOMPRESS_H #define __PLAT_UNCOMPRESS_H diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c index d53d75e..a56a067 100644 --- a/arch/arm/plat-spear/pl080.c +++ b/arch/arm/plat-spear/pl080.c @@ -17,6 +17,7 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/spinlock_types.h> +#include <mach/spear.h> #include <mach/misc_regs.h> static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x); diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c index 16f203e..4471a23 100644 --- a/arch/arm/plat-spear/restart.c +++ b/arch/arm/plat-spear/restart.c @@ -13,7 +13,7 @@ #include <linux/io.h> #include <asm/system_misc.h> #include <asm/hardware/sp810.h> -#include <mach/hardware.h> +#include <mach/spear.h> #include <mach/generic.h> void spear_restart(char mode, const char *cmd) diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c index 1c94989..03321af 100644 --- a/arch/arm/plat-spear/time.c +++ b/arch/arm/plat-spear/time.c @@ -15,14 +15,15 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/interrupt.h> +#include <linux/ioport.h> #include <linux/io.h> #include <linux/kernel.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> #include <linux/time.h> #include <linux/irq.h> #include <asm/mach/time.h> #include <mach/generic.h> -#include <mach/hardware.h> -#include <mach/irqs.h> /* * We would use TIMER0 and TIMER1 as clockevent and clocksource. @@ -175,7 +176,7 @@ static struct irqaction spear_timer_irq = { .handler = spear_timer_interrupt }; -static void __init spear_clockevent_init(void) +static void __init spear_clockevent_init(int irq) { u32 tick_rate; @@ -195,22 +196,35 @@ static void __init spear_clockevent_init(void) clockevents_register_device(&clkevt); - setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq); + setup_irq(irq, &spear_timer_irq); } -void __init spear_setup_timer(void) +const static struct of_device_id timer_of_match[] __initconst = { + { .compatible = "st,spear-timer", }, + { }, +}; + +void __init spear_setup_of_timer(void) { - int ret; + struct device_node *np; + int irq, ret; + + np = of_find_matching_node(NULL, timer_of_match); + if (!np) { + pr_err("%s: No timer passed via DT\n", __func__); + return; + } - if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) { - pr_err("%s:cannot get IO addr\n", __func__); + irq = irq_of_parse_and_map(np, 0); + if (!irq) { + pr_err("%s: No irq passed for timer via DT\n", __func__); return; } - gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K); + gpt_base = of_iomap(np, 0); if (!gpt_base) { - pr_err("%s:ioremap failed for gpt\n", __func__); - goto err_mem; + pr_err("%s: of iomap failed\n", __func__); + return; } gpt_clk = clk_get_sys("gpt0", NULL); @@ -225,7 +239,7 @@ void __init spear_setup_timer(void) goto err_prepare_enable_clk; } - spear_clockevent_init(); + spear_clockevent_init(irq); spear_clocksource_init(); return; @@ -234,6 +248,4 @@ err_prepare_enable_clk: clk_put(gpt_clk); err_iomap: iounmap(gpt_base); -err_mem: - release_mem_region(SPEAR_GPT0_BASE, SZ_1K); } diff --git a/drivers/of/address.c b/drivers/of/address.c index 66d96f1..7e262a6 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -1,4 +1,5 @@ +#include <linux/device.h> #include <linux/io.h> #include <linux/ioport.h> #include <linux/module.h> |
