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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2018-03-06 17:15:31 +0000
committerWill Deacon <will.deacon@arm.com>2018-03-08 13:49:26 +0000
commit5e8307b9c6f40526f290663e5a4de0f78bb0446a (patch)
tree405c3d4fbb2083f6141061faa5b8acd0cf5b7331
parente03e61c3173c1079058920210ab40c458a0e0899 (diff)
downloadop-kernel-dev-5e8307b9c6f40526f290663e5a4de0f78bb0446a.zip
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arm64: module: don't BUG when exceeding preallocated PLT count
When PLTs are emitted at relocation time, we really should not exceed the number that we counted when parsing the relocation tables, and so currently, we BUG() on this condition. However, even though this is a clear bug in this particular piece of code, we can easily recover by failing to load the module. So instead, return 0 from module_emit_plt_entry() if this condition occurs, which is not a valid kernel address, and can hence serve as a flag value that makes the relocation routine bail out. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
-rw-r--r--arch/arm64/kernel/module-plts.c3
-rw-r--r--arch/arm64/kernel/module.c2
2 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm64/kernel/module-plts.c b/arch/arm64/kernel/module-plts.c
index ea640f9..6bf07c6 100644
--- a/arch/arm64/kernel/module-plts.c
+++ b/arch/arm64/kernel/module-plts.c
@@ -36,7 +36,8 @@ u64 module_emit_plt_entry(struct module *mod, void *loc, const Elf64_Rela *rela,
return (u64)&plt[i - 1];
pltsec->plt_num_entries++;
- BUG_ON(pltsec->plt_num_entries > pltsec->plt_max_entries);
+ if (WARN_ON(pltsec->plt_num_entries > pltsec->plt_max_entries))
+ return 0;
return (u64)&plt[i];
}
diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c
index f469e04..c8c6c28 100644
--- a/arch/arm64/kernel/module.c
+++ b/arch/arm64/kernel/module.c
@@ -386,6 +386,8 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
ovf == -ERANGE) {
val = module_emit_plt_entry(me, loc, &rel[i], sym);
+ if (!val)
+ return -ENOEXEC;
ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2,
26, AARCH64_INSN_IMM_26);
}
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