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authorYixun Lan <yixun.lan@amlogic.com>2018-03-28 11:01:29 +0800
committerKevin Hilman <khilman@baylibre.com>2018-05-09 15:14:50 -0700
commit5e395e146667ef5484e7186d5a9218ce52b548d7 (patch)
treea75ccaf9f0bcd07b025c15b559b1080b35420a4f
parent0df8fbb9df8b73aafde80e1b1519a244ea703cf8 (diff)
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op-kernel-dev-5e395e146667ef5484e7186d5a9218ce52b548d7.tar.gz
ARM64: dts: meson-axg: add an 32K alt aoclk
The ao_clk81 in AO domain have two clock source, one from a 32K alt crystal we name it as ao_alt_clk, another is the clk81 signal from EE domain. Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-axg.dtsi7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 854d5b2..a3a0fd5 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -108,6 +108,13 @@
#clock-cells = <0>;
};
+ ao_alt_xtal: ao_alt_xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000000>;
+ clock-output-names = "ao_alt_xtal";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
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