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| author | Thierry Reding <treding@nvidia.com> | 2017-11-01 15:59:44 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-15 10:14:17 +0100 |
| commit | 50f5b841ba06f4dfb739e7a5ab9b87e8173d5915 (patch) | |
| tree | 5f1708c0c2a4eb8051b359c95ebe9f51763d0b95 | |
| parent | 102ca26a62e61e54abf41b3fc51038b4be80f197 (diff) | |
| download | op-kernel-dev-50f5b841ba06f4dfb739e7a5ab9b87e8173d5915.zip op-kernel-dev-50f5b841ba06f4dfb739e7a5ab9b87e8173d5915.tar.gz | |
arm64: tegra: Use sor1_out clock
Use the sor1_out clock instead of sor1_src. This is a more accurate
model of the hardware and allows for more complicated configurations
such as HDMI 2.0.
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra210.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 9bdf19f..9c24021 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -266,11 +266,11 @@ reg = <0x0 0x54580000 0x0 0x00040000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_SOR1_SRC>, + <&tegra_car TEGRA210_CLK_SOR1_OUT>, <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, <&tegra_car TEGRA210_CLK_PLL_DP>, <&tegra_car TEGRA210_CLK_SOR_SAFE>; - clock-names = "sor", "source", "parent", "dp", "safe"; + clock-names = "sor", "out", "parent", "dp", "safe"; resets = <&tegra_car 183>; reset-names = "sor"; pinctrl-0 = <&state_dpaux1_aux>; |
