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| author | James Hogan <james.hogan@imgtec.com> | 2017-03-14 10:25:45 +0000 |
|---|---|---|
| committer | James Hogan <james.hogan@imgtec.com> | 2017-03-28 15:36:17 +0100 |
| commit | 4fa9de5a645a9770679032a7eea0604f9a36eaf3 (patch) | |
| tree | 83d3672e5b49129a7843d0c093cd543fe0499994 | |
| parent | 7d8a528d19815e57566d1e2277f9535e43f4cb68 (diff) | |
| download | op-kernel-dev-4fa9de5a645a9770679032a7eea0604f9a36eaf3.zip op-kernel-dev-4fa9de5a645a9770679032a7eea0604f9a36eaf3.tar.gz | |
KVM: MIPS/Emulate: Adapt T&E CACHE emulation for Octeon
Cache management is implemented separately for Cavium Octeon CPUs, so
r4k_blast_[id]cache aren't available. Instead for Octeon perform a local
icache flush using local_flush_icache_range(), and for other platforms
which don't use c-r4k.c use __flush_cache_all() / flush_icache_all().
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <david.daney@cavium.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
| -rw-r--r-- | arch/mips/kvm/emulate.c | 30 | ||||
| -rw-r--r-- | arch/mips/mm/cache.c | 1 |
2 files changed, 28 insertions, 3 deletions
diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c index 2070864..4833eba 100644 --- a/arch/mips/kvm/emulate.c +++ b/arch/mips/kvm/emulate.c @@ -1833,11 +1833,35 @@ enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst, vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base, arch->gprs[base], offset); - if (cache == Cache_D) + if (cache == Cache_D) { +#ifdef CONFIG_CPU_R4K_CACHE_TLB r4k_blast_dcache(); - else if (cache == Cache_I) +#else + switch (boot_cpu_type()) { + case CPU_CAVIUM_OCTEON3: + /* locally flush icache */ + local_flush_icache_range(0, 0); + break; + default: + __flush_cache_all(); + break; + } +#endif + } else if (cache == Cache_I) { +#ifdef CONFIG_CPU_R4K_CACHE_TLB r4k_blast_icache(); - else { +#else + switch (boot_cpu_type()) { + case CPU_CAVIUM_OCTEON3: + /* locally flush icache */ + local_flush_icache_range(0, 0); + break; + default: + flush_icache_all(); + break; + } +#endif + } else { kvm_err("%s: unsupported CACHE INDEX operation\n", __func__); return EMULATE_FAIL; diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 6db3413..899e462 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -24,6 +24,7 @@ /* Cache operations. */ void (*flush_cache_all)(void); void (*__flush_cache_all)(void); +EXPORT_SYMBOL_GPL(__flush_cache_all); void (*flush_cache_mm)(struct mm_struct *mm); void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, unsigned long end); |
