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authorHeiko Stuebner <heiko@sntech.de>2015-08-05 00:14:55 +0200
committerHeiko Stuebner <heiko@sntech.de>2015-08-06 13:05:09 +0200
commit41fe6a01726b79b8531fed0a94b55d89a69ea5ee (patch)
treea79cf9b31e0924a9f4a13c40af8a5f3138efbe50
parentcb8cc37f4d38d96552f2c52deb15e511cdacf906 (diff)
downloadop-kernel-dev-41fe6a01726b79b8531fed0a94b55d89a69ea5ee.zip
op-kernel-dev-41fe6a01726b79b8531fed0a94b55d89a69ea5ee.tar.gz
ARM: rockchip: rename osc_switch_to_32k variable
The variable name is misleading, as the deep suspend mode always switches the main supplying clock to the 32kHz source. Additionally the main oscillator remains running in some cases, which this var indicates. So rename it to osc_disable to clarity. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
-rw-r--r--arch/arm/mach-rockchip/pm.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index 892bace..2ca1170 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -96,7 +96,7 @@ static bool rk3288_slp_disable_osc(void)
static void rk3288_slp_mode_set(int level)
{
u32 mode_set, mode_set1;
- bool osc_switch_to_32k = rk3288_slp_disable_osc();
+ bool osc_disable = rk3288_slp_disable_osc();
regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0);
regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
@@ -140,7 +140,7 @@ static void rk3288_slp_mode_set(int level)
BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |
BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);
- if (osc_switch_to_32k)
+ if (osc_disable)
mode_set |= BIT(PMU_OSC_24M_DIS);
mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
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