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authorBjorn Helgaas <bhelgaas@google.com>2016-10-11 08:33:33 -0500
committerBjorn Helgaas <bhelgaas@google.com>2016-10-11 08:33:58 -0500
commit3d469939bcdf044d9f370be4f6bf21436afea310 (patch)
treea9e09051ca882bcc40803b516d53e0a9f0b0286d
parent8ad750193430668d1d833dbee94788533b417b9a (diff)
downloadop-kernel-dev-3d469939bcdf044d9f370be4f6bf21436afea310.zip
op-kernel-dev-3d469939bcdf044d9f370be4f6bf21436afea310.tar.gz
PCI: designware: Uninline register accessors
The register accessors are not performance critical and small enough that the compiler can inline them itself if it makes sense. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--drivers/pci/host/pcie-designware.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index b8feea4..7a3458d 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -157,14 +157,14 @@ void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val)
writel(val, pp->dbi_base + reg);
}
-static inline u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg)
+static u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg)
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
return dw_pcie_readl_rc(pp, offset + reg);
}
-static inline void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index,
+static void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index,
u32 val, u32 reg)
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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