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authorRoshan Pius <rpius@chromium.org>2015-02-02 14:55:38 -0800
committerFelipe Balbi <balbi@ti.com>2015-02-04 11:16:47 -0600
commit251a17f5aff990ab117590df2a13ef032464c0d3 (patch)
treecbff9700882e16cf3186cfbb67faf73d71a98c96
parent1fa2df0c70dadba1139c9dd52c9070d00fe23c98 (diff)
downloadop-kernel-dev-251a17f5aff990ab117590df2a13ef032464c0d3.zip
op-kernel-dev-251a17f5aff990ab117590df2a13ef032464c0d3.tar.gz
usb: dwc2: Fix a bug in reading the endpoint directions from reg.
According to the DWC2 datasheet, the HWCFG1 register stores the configured endpoint directions for endpoints 0-15 in bit positions 0-31. ========================== Endpoint Direction (EpDir) This 32-bit field uses two bits per endpoint to determine the endpoint direction. Endpoint Bits [31:30]: Endpoint 15 direction Bits [29:28]: Endpoint 14 direction .... Bits [3:2]: Endpoint 1 direction Bits[1:0]: Endpoint 0 direction (always BIDIR) ========================== The DWC2 driver is currently interpreting the contents of the register as directions for endpoints 1-15 which leads to an error in determining the configured endpoint directions in the core because the first 2 bits determine the direction of endpoint 0 and not 1. This is based on testing/next branch in Felipe's git. Signed-off-by: Roshan Pius <rpius@chromium.org> Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
-rw-r--r--drivers/usb/dwc2/gadget.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 15aa578..6a30887 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -3308,7 +3308,7 @@ static int s3c_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
hsotg->eps_out[0] = hsotg->eps_in[0];
cfg = readl(hsotg->regs + GHWCFG1);
- for (i = 1; i < hsotg->num_of_eps; i++, cfg >>= 2) {
+ for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
ep_type = cfg & 3;
/* Direction in or both */
if (!(ep_type & 2)) {
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