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authorSean Wang <sean.wang@mediatek.com>2018-02-18 03:54:44 +0800
committerMatthias Brugger <matthias.bgg@gmail.com>2018-03-11 20:31:11 +0100
commit23beb1adb5f625e66bae442892c9e6c4720895c6 (patch)
tree9936439752b68e8e1df3cff159ce9bb5bd673187
parentae457b7679c4175115c58ec90b36f9ecc855731c (diff)
downloadop-kernel-dev-23beb1adb5f625e66bae442892c9e6c4720895c6.zip
op-kernel-dev-23beb1adb5f625e66bae442892c9e6c4720895c6.tar.gz
arm64: dts: mt7622: add flash related device nodes
add nodes for NOR flash, parallel Nand flash with error correction code support. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Cc: RogerCC Lin <rogercc.lin@mediatek.com> Cc: Guochun Mao <guochun.mao@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
-rw-r--r--arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts21
-rw-r--r--arch/arm64/boot/dts/mediatek/mt7622.dtsi34
2 files changed, 55 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index ba6a79c..48c5ba4 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -235,6 +235,10 @@
};
};
+&bch {
+ status = "disabled";
+};
+
&btif {
status = "okay";
};
@@ -257,6 +261,23 @@
status = "okay";
};
+&nandc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&parallel_nand_pins>;
+ status = "disabled";
+};
+
+&nor_flash {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_nor_pins>;
+ status = "disabled";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ };
+};
+
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm7_pins>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 755b1c5..e358eeb 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -468,6 +468,40 @@
status = "disabled";
};
+ nandc: nfi@1100d000 {
+ compatible = "mediatek,mt7622-nfc";
+ reg = <0 0x1100D000 0 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "pad_clk";
+ ecc-engine = <&bch>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ bch: ecc@1100e000 {
+ compatible = "mediatek,mt7622-ecc";
+ reg = <0 0x1100e000 0 0x1000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFIECC_PD>;
+ clock-names = "nfiecc_clk";
+ status = "disabled";
+ };
+
+ nor_flash: spi@11014000 {
+ compatible = "mediatek,mt7622-nor",
+ "mediatek,mt8173-nor";
+ reg = <0 0x11014000 0 0xe0>;
+ clocks = <&pericfg CLK_PERI_FLASH_PD>,
+ <&topckgen CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
spi1: spi@11016000 {
compatible = "mediatek,mt7622-spi";
reg = <0 0x11016000 0 0x100>;
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