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authorTomasz Nowicki <tomasz.nowicki@linaro.org>2015-05-26 20:49:15 +0800
committerBjorn Helgaas <bhelgaas@google.com>2015-12-10 19:38:06 -0600
commit21461775f3d173dedec27a0402d426ba422d80a1 (patch)
treefab34b6461867bf2db8b5cf1c3595a7107b88546
parent4066df6345f5b3bacdf7944c4d9a839f1eef5773 (diff)
downloadop-kernel-dev-21461775f3d173dedec27a0402d426ba422d80a1.zip
op-kernel-dev-21461775f3d173dedec27a0402d426ba422d80a1.tar.gz
x86/PCI: Clarify AMD Fam10h config access restrictions comment
Clarify the comment about AMD Fam10h config access restrictions, fix typos, and add a reference to the specification. [bhelgaas: streamline] Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
-rw-r--r--arch/x86/include/asm/pci_x86.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index fa1195d..46873fb 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -151,11 +151,11 @@ extern struct list_head pci_mmcfg_list;
#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
/*
- * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
- * on their northbrige except through the * %eax register. As such, you MUST
- * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
- * accessor functions.
- * In fact just use pci_config_*, nothing else please.
+ * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use
+ * %eax. No other source or target registers may be used. The following
+ * mmio_config_* accessors enforce this. See "BIOS and Kernel Developer's
+ * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1,
+ * "MMIO Configuration Coding Requirements".
*/
static inline unsigned char mmio_config_readb(void __iomem *pos)
{
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