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| author | Sudeep Holla <sudeep.holla@arm.com> | 2016-12-13 14:24:53 +0000 |
|---|---|---|
| committer | Sudeep Holla <sudeep.holla@arm.com> | 2016-12-30 15:31:24 +0000 |
| commit | 1dff32d7df7ff5d80194ebce7ab5755b32564e13 (patch) | |
| tree | c53691a74ed5d06c6fd294f96441b481c581cafb | |
| parent | 7ce7d89f48834cefece7804d38fc5d85382edf77 (diff) | |
| download | op-kernel-dev-1dff32d7df7ff5d80194ebce7ab5755b32564e13.zip op-kernel-dev-1dff32d7df7ff5d80194ebce7ab5755b32564e13.tar.gz | |
arm64: dts: vexpress: Support GICC_DIR operations
The GICv2 CPU interface registers span across 8K, not 4K as indicated in
the DT. Only the GICC_DIR register is located after the initial 4K
boundary, leaving a functional system but without support for separately
EOI'ing and deactivating interrupts.
After this change the system supports split priority drop and interrupt
deactivation. This patch is based on similar one from Christoffer Dall:
commit 368400e242dc ("ARM: dts: vexpress: Support GICC_DIR operations")
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| -rw-r--r-- | arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts index a852e28..a83ed2c 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts +++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts @@ -81,7 +81,7 @@ #address-cells = <0>; interrupt-controller; reg = <0x0 0x2c001000 0 0x1000>, - <0x0 0x2c002000 0 0x1000>, + <0x0 0x2c002000 0 0x2000>, <0x0 0x2c004000 0 0x2000>, <0x0 0x2c006000 0 0x2000>; interrupts = <1 9 0xf04>; |
