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authorAlexandru M Stan <amstan@chromium.org>2014-11-26 17:30:26 -0800
committerHeiko Stuebner <heiko@sntech.de>2014-11-28 00:40:53 +0100
commitc1c9f2cced4e3ba22b3fc25603dd3bd2ec7dc173 (patch)
tree0995e5a9525403a4df9ddf1d4373e36743fcf9a1
parent6d288b169bdfbed28d308b077af3d9196025cd8b (diff)
downloadop-kernel-dev-c1c9f2cced4e3ba22b3fc25603dd3bd2ec7dc173.zip
op-kernel-dev-c1c9f2cced4e3ba22b3fc25603dd3bd2ec7dc173.tar.gz
clk: rockchip: add bindings for the mmc clocks
These clocks represent the physical clocks (including phases) and they will later be used for clock phase tuning. Suggested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index edf0110..f60ce72 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -72,6 +72,14 @@
#define SCLK_HEVC_CABAC 111
#define SCLK_HEVC_CORE 112
#define SCLK_I2S0_OUT 113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO0_DRV 115
+#define SCLK_SDIO1_DRV 116
+#define SCLK_EMMC_DRV 117
+#define SCLK_SDMMC_SAMPLE 118
+#define SCLK_SDIO0_SAMPLE 119
+#define SCLK_SDIO1_SAMPLE 120
+#define SCLK_EMMC_SAMPLE 121
#define DCLK_VOP0 190
#define DCLK_VOP1 191
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