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| author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2013-06-06 11:21:23 +0200 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2013-06-06 19:09:00 +0000 |
| commit | 5f1f3d5088316f827591764aa6a5e7161eb514bd (patch) | |
| tree | 9ed6528b33dd6051d63ed304eeb040956cb27b86 | |
| parent | 4089fe95bfed295c8ad38251d5fe02b6b0ba684c (diff) | |
| download | op-kernel-dev-5f1f3d5088316f827591764aa6a5e7161eb514bd.zip op-kernel-dev-5f1f3d5088316f827591764aa6a5e7161eb514bd.tar.gz | |
arm: mvebu: armada-xp-{gp,openblocks-ax3-4}: specify PCIe range
The ranges DT entry needed by the PCIe controller is defined at the
SoC .dtsi level. However, some boards have a NOR flash, and to support
it, they need to override the SoC-level ranges property to add an
additional range. Since PCIe and NOR support came separately, some
boards were not properly changed to include the PCIe range in their
ranges property at the .dts level.
This commit fixes those platforms.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| -rw-r--r-- | arch/arm/boot/dts/armada-xp-gp.dts | 5 | ||||
| -rw-r--r-- | arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 5 |
2 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 3ee63d1..76db557 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -39,8 +39,9 @@ }; soc { - ranges = <0 0 0xd0000000 0x100000 - 0xf0000000 0 0xf0000000 0x1000000>; + ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ + 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ + 0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>; internal-regs { serial@12000 { diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 46b7850..fdea75c 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -27,8 +27,9 @@ }; soc { - ranges = <0 0 0xd0000000 0x100000 - 0xf0000000 0 0xf0000000 0x8000000>; + ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ + 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ + 0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>; internal-regs { serial@12000 { |
