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| author | Shawn Guo <shawn.guo@linaro.org> | 2012-10-15 16:48:04 +0800 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2012-10-16 10:07:04 -0700 |
| commit | 3d76f9f5d3f6c88c576ebd92c3e2edb6d6a27e6f (patch) | |
| tree | d66d98bad5cd50c85690dc71ceef56f476120f66 | |
| parent | 5448a279ebf2a8e4cc7289ff1ef382b3e71b8ea6 (diff) | |
| download | op-kernel-dev-3d76f9f5d3f6c88c576ebd92c3e2edb6d6a27e6f.zip op-kernel-dev-3d76f9f5d3f6c88c576ebd92c3e2edb6d6a27e6f.tar.gz | |
ARM: dts: imx6q-arm2: move NANDF_CS pins out of 'hog'
Commit 9e3c0066 (ARM: dts: imx6q-arm2: add pinctrl for uart and enet)
defines NANDF_CS pins as gpio in 'hog', assuming these two pins are
always used by usdhc3 in gpio mode as card-detection and
write-protection on ARM2 board. But it's not true. These pins are
shared by usdhc3 and gpmi-nand. We should have the pins functional
for gpmi-nand when usdhc3 is disabled.
Move the pins out of 'hog', so that pins only work in gpio mode as CD
and WP when usdhc3 is enabled, and otherwise they are available for
gpmi-nand.
Reported-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
| -rw-r--r-- | arch/arm/boot/dts/imx6q-arm2.dts | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index 15df4c1..5bfa02a 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -37,6 +37,13 @@ pinctrl_hog: hoggrp { fsl,pins = < 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */ + >; + }; + }; + + arm2 { + pinctrl_usdhc3_arm2: usdhc3grp-arm2 { + fsl,pins = < 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */ 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */ >; @@ -58,7 +65,8 @@ wp-gpios = <&gpio6 14 0>; vmmc-supply = <®_3p3v>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-0 = <&pinctrl_usdhc3_1 + &pinctrl_usdhc3_arm2>; status = "okay"; }; |
