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author | Andrew Jackson <Andrew.Jackson@arm.com> | 2014-11-07 12:10:44 +0000 |
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committer | Wolfram Sang <wsa@the-dreams.de> | 2014-11-21 08:06:32 +0100 |
commit | d39f77b06a712fcba6185a20bb209e357923d980 (patch) | |
tree | 96a079b1aec111f9a8c5f526f1197c3ceebbc296 | |
parent | 27caca9d2e01c92b26d0690f065aad093fea01c7 (diff) | |
download | op-kernel-dev-d39f77b06a712fcba6185a20bb209e357923d980.zip op-kernel-dev-d39f77b06a712fcba6185a20bb209e357923d980.tar.gz |
i2c: designware: prevent early stop on TX FIFO empty
If the Designware core is configured with IC_EMPTYFIFO_HOLD_MASTER_EN
set to zero, allowing the TX FIFO to become empty causes a STOP
condition to be generated on the I2C bus. If the transmit FIFO
threshold is set too high, an erroneous STOP condition can be
generated on long transfers - particularly where the interrupt
latency is extended.
Signed-off-by: Andrew Jackson <Andrew.Jackson@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
-rw-r--r-- | drivers/i2c/busses/i2c-designware-core.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c index edca99d..23628b7 100644 --- a/drivers/i2c/busses/i2c-designware-core.c +++ b/drivers/i2c/busses/i2c-designware-core.c @@ -359,7 +359,7 @@ int i2c_dw_init(struct dw_i2c_dev *dev) } /* Configure Tx/Rx FIFO threshold levels */ - dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); + dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL); dw_writel(dev, 0, DW_IC_RX_TL); /* configure the i2c master */ |