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| author | Alex Deucher <alexander.deucher@amd.com> | 2014-11-07 13:19:17 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2014-11-12 11:56:42 -0500 |
| commit | 36654dd4b9b9dd65143095ca48f5b9c846b13e0b (patch) | |
| tree | 22a3779c157aad85b798916f8ee7abc10b5b02cf | |
| parent | 127e056e2a82406fd3455a9da20d02f192ae8a05 (diff) | |
| download | op-kernel-dev-36654dd4b9b9dd65143095ca48f5b9c846b13e0b.zip op-kernel-dev-36654dd4b9b9dd65143095ca48f5b9c846b13e0b.tar.gz | |
drm/radeon: workaround a hw bug in bonaire pcie dpm
Some boards get stuck in pcie x1 otherwise.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/radeon/ci_dpm.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index a33e2388..aad6477 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c @@ -2988,9 +2988,14 @@ static int ci_setup_default_pcie_tables(struct radeon_device *rdev) &pi->dpm_table.pcie_speed_table, SMU7_MAX_LEVELS_LINK); - ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, - pi->pcie_gen_powersaving.min, - pi->pcie_lane_powersaving.min); + if (rdev->family == CHIP_BONAIRE) + ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, + pi->pcie_gen_powersaving.min, + pi->pcie_lane_powersaving.max); + else + ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, + pi->pcie_gen_powersaving.min, + pi->pcie_lane_powersaving.min); ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, pi->pcie_gen_performance.min, pi->pcie_lane_performance.min); |
