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| author | Alexander Graf <agraf@suse.de> | 2012-05-10 03:58:50 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2012-05-16 15:02:11 +0200 |
| commit | 32c7dbfd479e73684b0d23fcb0a5cb04f19d86f4 (patch) | |
| tree | 6b64efd4aed00c5954db0e7fdfef90eb67753a98 | |
| parent | 56e13dbae3eddb1648e6e94ae251c83cdc8304e0 (diff) | |
| download | op-kernel-dev-32c7dbfd479e73684b0d23fcb0a5cb04f19d86f4.zip op-kernel-dev-32c7dbfd479e73684b0d23fcb0a5cb04f19d86f4.tar.gz | |
KVM: PPC: Book3S: PR: Fix hsrr code
When jumping back into the kernel to code that knows that it would be
using HSRR registers instead of SRR registers, we need to make sure we
pass it all information on where to jump to in HSRR registers.
Unfortunately, we used r10 to store the information to distinguish between
the HSRR and SRR case. That register got clobbered in between though,
rendering the later comparison invalid.
Instead, let's use cr1 to store this information. That way we don't
need yet another register and everyone's happy.
This fixes PR KVM on POWER7 bare metal for me.
Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | arch/powerpc/kvm/book3s_segment.S | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/powerpc/kvm/book3s_segment.S b/arch/powerpc/kvm/book3s_segment.S index 87cfc1d..6e6e9ce 100644 --- a/arch/powerpc/kvm/book3s_segment.S +++ b/arch/powerpc/kvm/book3s_segment.S @@ -197,8 +197,8 @@ kvmppc_interrupt: /* Save guest PC and MSR */ #ifdef CONFIG_PPC64 BEGIN_FTR_SECTION - mr r10, r12 - andi. r0,r12,0x2 + andi. r0, r12, 0x2 + cmpwi cr1, r0, 0 beq 1f mfspr r3,SPRN_HSRR0 mfspr r4,SPRN_HSRR1 @@ -345,8 +345,7 @@ no_dcbz32_off: #ifdef CONFIG_PPC64 BEGIN_FTR_SECTION - andi. r0,r10,0x2 - beq 1f + beq cr1, 1f mtspr SPRN_HSRR1, r6 mtspr SPRN_HSRR0, r8 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
