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authorAnjali Singhai Jain <anjali.singhai@intel.com>2015-06-05 12:20:32 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2015-08-05 16:53:46 -0700
commit0d8e14392f7697e5ee241d49fce3355f22406d3e (patch)
treed13a068e87b3dd9bf422b28ef63a471528921846
parent527274c78ea7e0cad8b44ea25509c42aa605634e (diff)
downloadop-kernel-dev-0d8e14392f7697e5ee241d49fce3355f22406d3e.zip
op-kernel-dev-0d8e14392f7697e5ee241d49fce3355f22406d3e.tar.gz
i40e: Add IWARP support for X722
X722 supports IWARP, this patch handles checking for PE critical errors. Since the driver doesn't support the IWARP interface for now, this patch just does bare minimum to log a message oif a PE critical error happens. Signed-off-by: Anjali Singhai Jain <anjali.singhai@intel.com> Signed-off-by: Catherine Sullivan <catherine.sullivan@intel.com> Tested-by: Jim Young <james.m.young@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_main.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
index d9cb87f3..3bb832a 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
@@ -2908,6 +2908,9 @@ static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
I40E_PFINT_ICR0_ENA_VFLR_MASK |
I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
+ if (pf->flags & I40E_FLAG_IWARP_ENABLED)
+ val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
+
if (pf->flags & I40E_FLAG_PTP)
val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
@@ -3198,6 +3201,13 @@ static irqreturn_t i40e_intr(int irq, void *data)
(icr0 & I40E_PFINT_ICR0_SWINT_MASK))
pf->sw_int_count++;
+ if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
+ (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
+ ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
+ icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
+ dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
+ }
+
/* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
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