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| author | Bard Liao <bardliao@realtek.com> | 2015-11-10 14:40:55 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-11-10 18:58:19 +0000 |
| commit | 2f64b6ed44c26eeb3d1bf5428936629cf552eda7 (patch) | |
| tree | b04ad87ce6b7b8259ee047945b20f81e243b640c | |
| parent | 6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f (diff) | |
| download | op-kernel-dev-2f64b6ed44c26eeb3d1bf5428936629cf552eda7.zip op-kernel-dev-2f64b6ed44c26eeb3d1bf5428936629cf552eda7.tar.gz | |
ASoC: rl6231: avoid using divisible by 3 for DMIC clk
Few codecs will meet no DMIC clock output issue when select a divided
number which is divisible by 3. To prevent this issue, the patch ignore
the numbers when calculating the DMIC clock divider.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | sound/soc/codecs/rl6231.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sound/soc/codecs/rl6231.c b/sound/soc/codecs/rl6231.c index aca479f..18b4292 100644 --- a/sound/soc/codecs/rl6231.c +++ b/sound/soc/codecs/rl6231.c @@ -80,6 +80,8 @@ int rl6231_calc_dmic_clk(int rate) } for (i = 0; i < ARRAY_SIZE(div); i++) { + if ((div[i] % 3) == 0) + continue; /* find divider that gives DMIC frequency below 3MHz */ if (3000000 * div[i] >= rate) return i; |
