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| author | Nicolin Chen <Guangyu.Chen@freescale.com> | 2014-04-18 17:32:08 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-04-18 15:05:30 +0100 |
| commit | 6ae6698276ca36f37afc2ad38054092021519ad4 (patch) | |
| tree | 6b50cce43f976708de578b7728c2e8fb790488e1 | |
| parent | c9eaa447e77efe77b7fa4c953bd62de8297fd6c5 (diff) | |
| download | op-kernel-dev-6ae6698276ca36f37afc2ad38054092021519ad4.zip op-kernel-dev-6ae6698276ca36f37afc2ad38054092021519ad4.tar.gz | |
ASoC: fsl_spdif: Fix wrong OFFSET of STC_SYSCLK_DIV
It should use STC_SYSCLK_DIV_OFFSET. Thus fix it.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
| -rw-r--r-- | sound/soc/fsl/fsl_spdif.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/fsl/fsl_spdif.h b/sound/soc/fsl/fsl_spdif.h index b126679..605a10b 100644 --- a/sound/soc/fsl/fsl_spdif.h +++ b/sound/soc/fsl/fsl_spdif.h @@ -144,8 +144,8 @@ enum spdif_gainsel { /* SPDIF Clock register */ #define STC_SYSCLK_DIV_OFFSET 11 -#define STC_SYSCLK_DIV_MASK (0x1ff << STC_TXCLK_SRC_OFFSET) -#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_SYSCLK_DIV_MASK) +#define STC_SYSCLK_DIV_MASK (0x1ff << STC_SYSCLK_DIV_OFFSET) +#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_SYSCLK_DIV_OFFSET) & STC_SYSCLK_DIV_MASK) #define STC_TXCLK_SRC_OFFSET 8 #define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET) #define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK) |
