diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2011-04-08 10:07:34 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2011-04-20 08:50:37 +1000 |
| commit | 01d153326ecd81ed77395f1699a30af416cf77ab (patch) | |
| tree | ef988a2e87ed82d40cc06a752dcdf139bb968ffa | |
| parent | 04eb34a43ce5168e05e2748bd46a62a09289cdde (diff) | |
| download | op-kernel-dev-01d153326ecd81ed77395f1699a30af416cf77ab.zip op-kernel-dev-01d153326ecd81ed77395f1699a30af416cf77ab.tar.gz | |
drm/nouveau: fix nv30 pcie boards
Wasn't aware they even existed, apparently they do! They're actually
AGP chips with a bridge as far as I can tell, which puts them in the
same boat as nv40/nv45.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_mem.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_sgdma.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index 78f467f..5045f8b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c @@ -398,7 +398,7 @@ nouveau_mem_vram_init(struct drm_device *dev) dma_bits = 40; } else if (drm_pci_device_is_pcie(dev) && - dev_priv->chipset != 0x40 && + dev_priv->chipset > 0x40 && dev_priv->chipset != 0x45) { if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39))) dma_bits = 39; diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c index a33fe40..fc29244 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c +++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c @@ -427,7 +427,7 @@ nouveau_sgdma_init(struct drm_device *dev) u32 aper_size, align; int ret; - if (dev_priv->card_type >= NV_50 || drm_pci_device_is_pcie(dev)) + if (dev_priv->card_type >= NV_40 && drm_pci_device_is_pcie(dev)) aper_size = 512 * 1024 * 1024; else aper_size = 64 * 1024 * 1024; @@ -457,7 +457,7 @@ nouveau_sgdma_init(struct drm_device *dev) dev_priv->gart_info.func = &nv50_sgdma_backend; } else if (drm_pci_device_is_pcie(dev) && - dev_priv->chipset != 0x40 && dev_priv->chipset != 0x45) { + dev_priv->chipset > 0x40 && dev_priv->chipset != 0x45) { if (nv44_graph_class(dev)) { dev_priv->gart_info.func = &nv44_sgdma_backend; align = 512 * 1024; |
