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| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-02-24 17:29:06 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-02-28 12:04:53 +0100 |
| commit | 225b02163cd51b6d5ebef4d2e19a09345f2ee3a5 (patch) | |
| tree | fc86d2f4c738b90de28828e662a7ef17353aaa1b | |
| parent | d5cf89c9ec7761e48e016460d26221533e2f6c7b (diff) | |
| download | op-kernel-dev-225b02163cd51b6d5ebef4d2e19a09345f2ee3a5.zip op-kernel-dev-225b02163cd51b6d5ebef4d2e19a09345f2ee3a5.tar.gz | |
ARM: sun6i: dt: Fix mod0 compatible
The module 0 clock compatibles were changed between the time the patch was sent
and it was merged. Update the compatibles.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| -rw-r--r-- | arch/arm/boot/dts/sun6i-a31.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index af6f87c..42f310a 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -200,7 +200,7 @@ spi0_clk: clk@01c200a0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a0 0x4>; clocks = <&osc24M>, <&pll6>; clock-output-names = "spi0"; @@ -208,7 +208,7 @@ spi1_clk: clk@01c200a4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a4 0x4>; clocks = <&osc24M>, <&pll6>; clock-output-names = "spi1"; @@ -216,7 +216,7 @@ spi2_clk: clk@01c200a8 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a8 0x4>; clocks = <&osc24M>, <&pll6>; clock-output-names = "spi2"; @@ -224,7 +224,7 @@ spi3_clk: clk@01c200ac { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200ac 0x4>; clocks = <&osc24M>, <&pll6>; clock-output-names = "spi3"; |
