summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAlexander Shiyan <shc_work@mail.ru>2014-05-08 11:56:38 +0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-06-19 17:43:34 -0700
commitb0dceb6a96c2f87a40a9f99bc05711a3f7c1eaa2 (patch)
tree8d3b6ac565360c27b91b44ae58dc987c7f0b2c9b
parent7cbcb136a7d703f1bd590979a3d07348fe1bc81d (diff)
downloadop-kernel-dev-b0dceb6a96c2f87a40a9f99bc05711a3f7c1eaa2.zip
op-kernel-dev-b0dceb6a96c2f87a40a9f99bc05711a3f7c1eaa2.tar.gz
w1: mxc_w1: Optimize mxc_w1_ds2_reset_bus()
According to the i.MX reference manual, the reset procedure and "presence" pulse takes 511 and 512 us, respectively. Measurement for i.MX27 is about 1100 us. There is no need to wait Reset+Presence more than this time. This patch optimizes mxc_w1_ds2_reset_bus() function to use proper value for delay after w1 bus reset. Nevertheless, a small margin for the timeout has been added for the case if clock frequency is inaccurate. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/w1/masters/mxc_w1.c32
1 files changed, 15 insertions, 17 deletions
diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c
index a5df5e8..0d05abe 100644
--- a/drivers/w1/masters/mxc_w1.c
+++ b/drivers/w1/masters/mxc_w1.c
@@ -15,16 +15,13 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "../w1.h"
#include "../w1_int.h"
-/* According to the mx27 Datasheet the reset procedure should take up to about
- * 1350us. We set the timeout to 500*100us = 50ms for sure */
-#define MXC_W1_RESET_TIMEOUT 500
-
/*
* MXC W1 Register offsets
*/
@@ -49,24 +46,25 @@ struct mxc_w1_device {
*/
static u8 mxc_w1_ds2_reset_bus(void *data)
{
- u8 reg_val;
- unsigned int timeout_cnt = 0;
struct mxc_w1_device *dev = data;
+ unsigned long timeout;
- writeb(MXC_W1_CONTROL_RPP, (dev->regs + MXC_W1_CONTROL));
+ writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL);
- while (1) {
- reg_val = readb(dev->regs + MXC_W1_CONTROL);
+ /* Wait for reset sequence 511+512us, use 1500us for sure */
+ timeout = jiffies + usecs_to_jiffies(1500);
- if (!(reg_val & MXC_W1_CONTROL_RPP) ||
- timeout_cnt > MXC_W1_RESET_TIMEOUT)
- break;
- else
- timeout_cnt++;
+ udelay(511 + 512);
- udelay(100);
- }
- return !(reg_val & MXC_W1_CONTROL_PST);
+ do {
+ u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
+
+ /* PST bit is valid after the RPP bit is self-cleared */
+ if (!(ctrl & MXC_W1_CONTROL_RPP))
+ return !(ctrl & MXC_W1_CONTROL_PST);
+ } while (time_is_after_jiffies(timeout));
+
+ return 1;
}
/*
OpenPOWER on IntegriCloud