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| author | Eric Anholt <eric@anholt.net> | 2008-09-15 13:13:34 -0700 |
|---|---|---|
| committer | Dave Airlie <airlied@linux.ie> | 2008-10-18 07:10:52 +1000 |
| commit | 28af0a2767412937e8424364a8ece9b230bdbc83 (patch) | |
| tree | e8883735390a123c0e88f53aa85568772d1e4d6a | |
| parent | 4f481ed22ec0d412336a13dc4477f6d0f3688882 (diff) | |
| download | op-kernel-dev-28af0a2767412937e8424364a8ece9b230bdbc83.zip op-kernel-dev-28af0a2767412937e8424364a8ece9b230bdbc83.tar.gz | |
drm: G33-class hardware has a newer 965-style MCH (no DCC register).
Fixes bad software fallback rendering in Mesa in dual-channel configurations.
d9a2470012588dc5313a5ac8bb2f03575af00e99
Signed-off-by: Dave Airlie <airlied@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_tiling.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index 0c1b3a08..6b3f1e4 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -96,7 +96,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) */ swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE; - } else if (!IS_I965G(dev) || IS_I965GM(dev)) { + } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) { uint32_t dcc; /* On 915-945 and GM965, channel interleave by the CPU is |
