diff options
author | Zachary Amsden <zach@vmware.com> | 2005-09-03 15:56:37 -0700 |
---|---|---|
committer | Linus Torvalds <torvalds@evo.osdl.org> | 2005-09-05 00:06:11 -0700 |
commit | 245067d1674d451855692fcd4647daf9fd47f82d (patch) | |
tree | 9e82ee9ce5c1899e0da06622716dffda02e94b15 | |
parent | 4bb0d3ec3e5b1e9e2399cdc641b3b6521ac9cdaa (diff) | |
download | op-kernel-dev-245067d1674d451855692fcd4647daf9fd47f82d.zip op-kernel-dev-245067d1674d451855692fcd4647daf9fd47f82d.tar.gz |
[PATCH] i386: cleanup serialize msr
i386 arch cleanup. Introduce the serialize macro to serialize processor
state. Why the microcode update needs it I am not quite sure, since wrmsr()
is already a serializing instruction, but it is a microcode update, so I will
keep the semantic the same, since this could be a timing workaround. As far
as I can tell, this has always been there since the original microcode update
source.
Signed-off-by: Zachary Amsden <zach@vmware.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r-- | arch/i386/kernel/microcode.c | 7 | ||||
-rw-r--r-- | include/asm-i386/processor.h | 5 | ||||
-rw-r--r-- | include/asm-x86_64/processor.h | 5 |
3 files changed, 15 insertions, 2 deletions
diff --git a/arch/i386/kernel/microcode.c b/arch/i386/kernel/microcode.c index a77c612..165f131 100644 --- a/arch/i386/kernel/microcode.c +++ b/arch/i386/kernel/microcode.c @@ -164,7 +164,8 @@ static void collect_cpu_info (void *unused) } wrmsr(MSR_IA32_UCODE_REV, 0, 0); - __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); + /* see notes above for revision 1.07. Apparent chip bug */ + serialize_cpu(); /* get the current revision from MSR 0x8B */ rdmsr(MSR_IA32_UCODE_REV, val[0], uci->rev); pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n", @@ -377,7 +378,9 @@ static void do_update_one (void * unused) (unsigned long) uci->mc->bits >> 16 >> 16); wrmsr(MSR_IA32_UCODE_REV, 0, 0); - __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); + /* see notes above for revision 1.07. Apparent chip bug */ + serialize_cpu(); + /* get the current revision from MSR 0x8B */ rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h index 7e17d3b..a0489b2 100644 --- a/include/asm-i386/processor.h +++ b/include/asm-i386/processor.h @@ -277,6 +277,11 @@ static inline void clear_in_cr4 (unsigned long mask) outb((data), 0x23); \ } while (0) +static inline void serialize_cpu(void) +{ + __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); +} + static inline void __monitor(const void *eax, unsigned long ecx, unsigned long edx) { diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h index 85549e6..194160f 100644 --- a/include/asm-x86_64/processor.h +++ b/include/asm-x86_64/processor.h @@ -437,6 +437,11 @@ static inline void prefetchw(void *x) outb((data), 0x23); \ } while (0) +static inline void serialize_cpu(void) +{ + __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); +} + static inline void __monitor(const void *eax, unsigned long ecx, unsigned long edx) { |