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| author | Jernej Skrabec <jernej.skrabec@siol.net> | 2018-03-01 22:34:27 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-03-02 08:42:14 +0100 |
| commit | 2d2b61c13a4b39c8ba6b9c1daa79d5891689864e (patch) | |
| tree | edc1c7a176a8e6c88b3f4ec3fd4a8a16801042b3 | |
| parent | a5ebc3368ef7c77da5a03ad52834520a634a36ef (diff) | |
| download | op-kernel-dev-2d2b61c13a4b39c8ba6b9c1daa79d5891689864e.zip op-kernel-dev-2d2b61c13a4b39c8ba6b9c1daa79d5891689864e.tar.gz | |
clk: sunxi-ng: Add check for minimal rate to NM PLLs
Some NM PLLs doesn't work well when their output clock rate is set below
certain rate.
Add support for that constrain.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu_nm.c | 7 | ||||
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu_nm.h | 27 |
2 files changed, 34 insertions, 0 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c index a16de09..4e20733 100644 --- a/drivers/clk/sunxi-ng/ccu_nm.c +++ b/drivers/clk/sunxi-ng/ccu_nm.c @@ -117,6 +117,13 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate, if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) rate *= nm->fixed_post_div; + if (rate < nm->min_rate) { + rate = nm->min_rate; + if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) + rate /= nm->fixed_post_div; + return rate; + } + if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) { if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) rate /= nm->fixed_post_div; diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h index eba586b..1d8b459 100644 --- a/drivers/clk/sunxi-ng/ccu_nm.h +++ b/drivers/clk/sunxi-ng/ccu_nm.h @@ -37,6 +37,7 @@ struct ccu_nm { struct ccu_sdm_internal sdm; unsigned int fixed_post_div; + unsigned int min_rate; struct ccu_common common; }; @@ -88,6 +89,32 @@ struct ccu_nm { }, \ } +#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent, \ + _reg, _min_rate, \ + _nshift, _nwidth, \ + _mshift, _mwidth, \ + _frac_en, _frac_sel, \ + _frac_rate_0, _frac_rate_1,\ + _gate, _lock, _flags) \ + struct ccu_nm _struct = { \ + .enable = _gate, \ + .lock = _lock, \ + .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \ + .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ + .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \ + _frac_rate_0, \ + _frac_rate_1), \ + .min_rate = _min_rate, \ + .common = { \ + .reg = _reg, \ + .features = CCU_FEATURE_FRACTIONAL, \ + .hw.init = CLK_HW_INIT(_name, \ + _parent, \ + &ccu_nm_ops, \ + _flags), \ + }, \ + } + #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ _nshift, _nwidth, \ _mshift, _mwidth, \ |
