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| author | Abel Gordon <abelg@il.ibm.com> | 2013-04-18 14:34:55 +0300 |
|---|---|---|
| committer | Gleb Natapov <gleb@redhat.com> | 2013-04-22 10:51:09 +0300 |
| commit | 89662e566c73230dab9f1d99dbe2f6d9c8c189a8 (patch) | |
| tree | f3a9fac467792d9ce01e74d32b0744afc0da3ef1 | |
| parent | d10ab869ae5f76231a729fbf575370bf76e4bcb8 (diff) | |
| download | op-kernel-dev-89662e566c73230dab9f1d99dbe2f6d9c8c189a8.zip op-kernel-dev-89662e566c73230dab9f1d99dbe2f6d9c8c189a8.tar.gz | |
KVM: nVMX: Shadow-vmcs control fields/bits
Add definitions for all the vmcs control fields/bits
required to enable vmcs-shadowing
Signed-off-by: Abel Gordon <abelg@il.ibm.com>
Reviewed-by: Orit Wasserman <owasserm@redhat.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
| -rw-r--r-- | arch/x86/include/asm/vmx.h | 3 | ||||
| -rw-r--r-- | arch/x86/include/uapi/asm/msr-index.h | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index 6f07f19..f3e01a2 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -65,6 +65,7 @@ #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 #define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 +#define SECONDARY_EXEC_SHADOW_VMCS 0x00004000 #define PIN_BASED_EXT_INTR_MASK 0x00000001 @@ -150,6 +151,8 @@ enum vmcs_field { EOI_EXIT_BITMAP2_HIGH = 0x00002021, EOI_EXIT_BITMAP3 = 0x00002022, EOI_EXIT_BITMAP3_HIGH = 0x00002023, + VMREAD_BITMAP = 0x00002026, + VMWRITE_BITMAP = 0x00002028, GUEST_PHYSICAL_ADDRESS = 0x00002400, GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401, VMCS_LINK_POINTER = 0x00002800, diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index 892ce40..dc469e3 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h @@ -522,6 +522,8 @@ #define VMX_BASIC_MEM_TYPE_WB 6LLU #define VMX_BASIC_INOUT 0x0040000000000000LLU +/* MSR_IA32_VMX_MISC bits */ +#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) /* AMD-V MSRs */ #define MSR_VM_CR 0xc0010114 |
