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| author | Jesse Brandeburg <jesse.brandeburg@intel.com> | 2006-08-16 13:47:25 -0700 |
|---|---|---|
| committer | Auke Kok <juke-jan.h.kok@intel.com> | 2006-08-16 13:47:25 -0700 |
| commit | 3ae84d9269592a1284892c93597a604a894f1102 (patch) | |
| tree | e6bb8f5adf7b944ff21b25b0a4586529efceeefb | |
| parent | 0fe198a5e10229b269624a18bbd390001a8d3476 (diff) | |
| download | op-kernel-dev-3ae84d9269592a1284892c93597a604a894f1102.zip op-kernel-dev-3ae84d9269592a1284892c93597a604a894f1102.tar.gz | |
ixgb: fix cache miss due to miscalculation
Reduce writeback threshold by 1. We were instructing the hardware to
wait until the 17th descriptor which went over the cache line limit.
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Auke Kok <auke.jan.h.kok@intel.com>
| -rw-r--r-- | drivers/net/ixgb/ixgb_main.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/net/ixgb/ixgb_main.c b/drivers/net/ixgb/ixgb_main.c index 7bbd447..770eef2 100644 --- a/drivers/net/ixgb/ixgb_main.c +++ b/drivers/net/ixgb/ixgb_main.c @@ -140,12 +140,12 @@ module_param(debug, int, 0); MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); /* some defines for controlling descriptor fetches in h/w */ -#define RXDCTL_WTHRESH_DEFAULT 16 /* chip writes back at this many or RXT0 */ -#define RXDCTL_PTHRESH_DEFAULT 0 /* chip considers prefech below - * this */ -#define RXDCTL_HTHRESH_DEFAULT 0 /* chip will only prefetch if tail - * is pushed this many descriptors - * from head */ +#define RXDCTL_WTHRESH_DEFAULT 15 /* chip writes back at this many or RXT0 */ +#define RXDCTL_PTHRESH_DEFAULT 0 /* chip considers prefech below + * this */ +#define RXDCTL_HTHRESH_DEFAULT 0 /* chip will only prefetch if tail + * is pushed this many descriptors + * from head */ /** * ixgb_init_module - Driver Registration Routine |
