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| author | Sudeep Holla <sudeep.holla@arm.com> | 2015-03-11 11:54:29 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2015-03-23 10:22:38 +0100 |
| commit | 37dea8c52cacb4439eb183ad736747bb678d2a5d (patch) | |
| tree | 5b46065e7e488e66c8753fe5bdd09d6be2c8f42d | |
| parent | cecae360744d958c0af562e806dbd4632be13efc (diff) | |
| download | op-kernel-dev-37dea8c52cacb4439eb183ad736747bb678d2a5d.zip op-kernel-dev-37dea8c52cacb4439eb183ad736747bb678d2a5d.tar.gz | |
x86/cpu/cacheinfo: Fix cache_get_priv_group() for Intel processors
The private pointer provided by the cacheinfo code is used to implement
the AMD L3 cache-specific attributes using a pointer to the northbridge
descriptor. It is needed for performing L3-specific operations and for
that we need a couple of PCI devices and other service information, all
contained in the northbridge descriptor.
This results in failure of cacheinfo setup as shown below as
cache_get_priv_group() returns the uninitialised private attributes which
are not valid for Intel processors.
------------[ cut here ]------------
WARNING: CPU: 3 PID: 1 at fs/sysfs/group.c:102
internal_create_group+0x151/0x280()
sysfs: (bin_)attrs not set by subsystem for group: index3/
Modules linked in:
CPU: 3 PID: 1 Comm: swapper/0 Not tainted 4.0.0-rc3+ #1
Hardware name: Dell Inc. Precision T3600/0PTTT9, BIOS A13 05/11/2014
...
Call Trace:
dump_stack
warn_slowpath_common
warn_slowpath_fmt
internal_create_group
sysfs_create_groups
device_add
cpu_device_create
? __kmalloc
cache_add_dev
cacheinfo_sysfs_init
? container_dev_init
do_one_initcall
kernel_init_freeable
? rest_init
kernel_init
ret_from_fork
? rest_init
This patch fixes the issue by checking if the L3 cache indices are
populated correctly (AMD-specific) before initializing the private
attributes.
Reported-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
| -rw-r--r-- | arch/x86/kernel/cpu/intel_cacheinfo.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 8008bc2..edcb0e2 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -556,7 +556,7 @@ cache_get_priv_group(struct cacheinfo *this_leaf) { struct amd_northbridge *nb = this_leaf->priv; - if (this_leaf->level < 3) + if (this_leaf->level < 3 || !nb) return NULL; if (nb && nb->l3_cache.indices) |
