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authorYazen Ghannam <yazen.ghannam@amd.com>2017-06-13 18:28:28 +0200
committerIngo Molnar <mingo@kernel.org>2017-06-14 07:32:06 +0200
commita24b8c3409935bbc8e3c12131c473c92692403cd (patch)
treeff76d636c1cccc4f1e38971881a4b4a807dba603
parent10b90ee2eccca042e2d762881dd7119d201f0898 (diff)
downloadop-kernel-dev-a24b8c3409935bbc8e3c12131c473c92692403cd.zip
op-kernel-dev-a24b8c3409935bbc8e3c12131c473c92692403cd.tar.gz
x86/mce/AMD: Use msr_stat when clearing MCA_STATUS
The value of MCA_STATUS is used as the MSR when clearing MCA_STATUS. This may cause the following warning: unchecked MSR access error: WRMSR to 0x11b (tried to write 0x0000000000000000) Call Trace: <IRQ> smp_threshold_interrupt() threshold_interrupt() Use msr_stat instead which has the MSR address. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Fixes: 37d43acfd79f ("x86/mce/AMD: Redo error logging from APIC LVT interrupt handlers") Link: http://lkml.kernel.org/r/20170613162835.30750-2-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_amd.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index d00f299..d11f94e 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -815,7 +815,7 @@ _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
__log_error(bank, status, addr, misc);
- wrmsrl(status, 0);
+ wrmsrl(msr_stat, 0);
return status & MCI_STATUS_DEFERRED;
}
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