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| author | Ben Widawsky <ben@bwidawsk.net> | 2011-03-19 18:14:28 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-05-10 13:56:41 -0700 |
| commit | 4a246cfc3c337ecb800d508ee5ed906534edb25c (patch) | |
| tree | 3430259d8dc22c6b80904d98dbdba39d23e6a831 | |
| parent | 96f298aa9c9fc9b7c8a2ebaf8c195d178f570e09 (diff) | |
| download | op-kernel-dev-4a246cfc3c337ecb800d508ee5ed906534edb25c.zip op-kernel-dev-4a246cfc3c337ecb800d508ee5ed906534edb25c.tar.gz | |
drm/i915: fix rc6 initialization on Ironlake
There is a race condition between setting PWRCTXA and executing
MI_SET_CONTEXT. PWRCTXA must not be set until a valid context has been
written (or else the GPU could possible go into rc6, and return to an
invalid context).
Reported-and-Tested-by: Gu Rui <chaos.proton@gmail.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=28582
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b6f593a..463f753 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7325,6 +7325,19 @@ void ironlake_enable_rc6(struct drm_device *dev) OUT_RING(MI_FLUSH); ADVANCE_LP_RING(); + /* + * Wait for the command parser to advance past MI_SET_CONTEXT. The HW + * does an implicit flush, combined with MI_FLUSH above, it should be + * safe to assume that renderctx is valid + */ + ret = intel_wait_ring_idle(LP_RING(dev_priv)); + if (ret) { + DRM_ERROR("failed to enable ironlake power power savings\n"); + ironlake_teardown_rc6(dev); + mutex_unlock(&dev->struct_mutex); + return; + } + I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); mutex_unlock(&dev->struct_mutex); |
