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| author | Philipp Zabel <p.zabel@pengutronix.de> | 2014-11-28 16:23:46 +0100 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2014-12-29 19:22:25 +0800 |
| commit | b2faf1a1aff945ec2abf2efdd9002c96b25378e8 (patch) | |
| tree | cba5f78824ba3045dc2da557a9c312cdb70c0a67 | |
| parent | 4fe6be0fe0c8bec2fdeafe11e7202679cd68e0b2 (diff) | |
| download | op-kernel-dev-b2faf1a1aff945ec2abf2efdd9002c96b25378e8.zip op-kernel-dev-b2faf1a1aff945ec2abf2efdd9002c96b25378e8.tar.gz | |
ARM: dts: imx6qdl: Fix CODA960 interrupt order
Commit a04a0b6fed4f ("ARM: dts: imx6qdl: Enable CODA960 VPU") lost the
fix for the CODA960 interrupt order during a rebase before being applied.
This patch adds the missing bit and brings the interrupts and
interrupt-names properties back in sync.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 4fc03b7..2109d07 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -335,8 +335,8 @@ vpu: vpu@02040000 { compatible = "cnm,coda960"; reg = <0x02040000 0x3c000>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, - <0 12 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "bit", "jpeg"; clocks = <&clks IMX6QDL_CLK_VPU_AXI>, <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, |
