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| author | Fabio Estevam <fabio.estevam@freescale.com> | 2013-07-04 20:01:03 -0300 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2013-07-05 10:45:49 +0100 |
| commit | 5c78dfe87ea04b501ee000a7f03b9432ac9d008c (patch) | |
| tree | 3e7c444077cf12eb4fa0ecebc18534979036f46f | |
| parent | 016fcab8ff46fca29375d484226ec91932aa4a07 (diff) | |
| download | op-kernel-dev-5c78dfe87ea04b501ee000a7f03b9432ac9d008c.zip op-kernel-dev-5c78dfe87ea04b501ee000a7f03b9432ac9d008c.tar.gz | |
ASoC: sglt5000: Fix SGTL5000_PLL_FRAC_DIV_MASK
SGTL5000_PLL_FRAC_DIV_MASK is used to mask bits 0-10 (11 bits in total) of
register CHIP_PLL_CTRL, so fix the mask to accomodate all this bit range.
Reported-by: Oskar Schirmer <oskar@scara.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Cc: stable@vger.kernel.org
| -rw-r--r-- | sound/soc/codecs/sgtl5000.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/codecs/sgtl5000.h b/sound/soc/codecs/sgtl5000.h index 4b69229..2f8c889 100644 --- a/sound/soc/codecs/sgtl5000.h +++ b/sound/soc/codecs/sgtl5000.h @@ -347,7 +347,7 @@ #define SGTL5000_PLL_INT_DIV_MASK 0xf800 #define SGTL5000_PLL_INT_DIV_SHIFT 11 #define SGTL5000_PLL_INT_DIV_WIDTH 5 -#define SGTL5000_PLL_FRAC_DIV_MASK 0x0700 +#define SGTL5000_PLL_FRAC_DIV_MASK 0x07ff #define SGTL5000_PLL_FRAC_DIV_SHIFT 0 #define SGTL5000_PLL_FRAC_DIV_WIDTH 11 |
