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authorMaciej W. Rozycki <macro@linux-mips.org>2015-06-02 17:50:59 +0100
committerRalf Baechle <ralf@linux-mips.org>2015-06-03 09:50:29 +0200
commit90b712ddabb40c49ca4f68bab07e27aa34c8d2a3 (patch)
tree41550c30a72b279e9c51cebe5a92c16f08302bbe
parenta26484bb7e77d474ecef1ef01ce37fb16fb84f60 (diff)
downloadop-kernel-dev-90b712ddabb40c49ca4f68bab07e27aa34c8d2a3.zip
op-kernel-dev-90b712ddabb40c49ca4f68bab07e27aa34c8d2a3.tar.gz
MIPS: Avoid an FPE exception in FCSR mask probing
Use the default FCSR value in mask probing, avoiding an FPE exception where reset has left any exception enable and their corresponding cause bits set and the register is then rewritten with these bits active. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Joshua Kinard <kumba@gentoo.org> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/kernel/cpu-probe.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index e36515d..209e5b7 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -74,13 +74,12 @@ static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
{
unsigned long sr, mask, fcsr, fcsr0, fcsr1;
+ fcsr = c->fpu_csr31;
mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
sr = read_c0_status();
__enable_fpu(FPU_AS_IS);
- fcsr = read_32bit_cp1_register(CP1_STATUS);
-
fcsr0 = fcsr & mask;
write_32bit_cp1_register(CP1_STATUS, fcsr0);
fcsr0 = read_32bit_cp1_register(CP1_STATUS);
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