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authorMarkos Chandras <markos.chandras@imgtec.com>2014-11-26 13:56:51 +0000
committerMarkos Chandras <markos.chandras@imgtec.com>2015-02-17 15:37:34 +0000
commit8467ca0122e20f3f8e73d34907b8b30461af5d4e (patch)
treeb2c543790a8035ff5bde5d8a93567459eca534c7
parentf1b44067c19258b7614e3cd09dfe8d8e12ff5895 (diff)
downloadop-kernel-dev-8467ca0122e20f3f8e73d34907b8b30461af5d4e.zip
op-kernel-dev-8467ca0122e20f3f8e73d34907b8b30461af5d4e.tar.gz
MIPS: Emulate the new MIPS R6 branch compact (BC) instruction
MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
-rw-r--r--arch/mips/include/uapi/asm/inst.h2
-rw-r--r--arch/mips/kernel/branch.c9
-rw-r--r--arch/mips/math-emu/cp1emu.c13
3 files changed, 23 insertions, 1 deletions
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 19d3bc1..9ce5e34 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -31,7 +31,7 @@ enum major_op {
lbu_op, lhu_op, lwr_op, lwu_op,
sb_op, sh_op, swl_op, sw_op,
sdl_op, sdr_op, swr_op, cache_op,
- ll_op, lwc1_op, lwc2_op, pref_op,
+ ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
lld_op, ldc1_op, ldc2_op, ld_op,
sc_op, swc1_op, swc2_op, major_3b_op,
scd_op, sdc1_op, sdc2_op, sd_op
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index cd880b9..1a0a30e 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -780,6 +780,15 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
epc += 8;
regs->cp0_epc = epc;
break;
+#else
+ case bc6_op:
+ /* Only valid for MIPS R6 */
+ if (!cpu_has_mips_r6) {
+ ret = -SIGILL;
+ break;
+ }
+ regs->cp0_epc += 8;
+ break;
#endif
}
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index d6d67e2..7f373a2 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -648,6 +648,19 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
else
*contpc = regs->cp0_epc + 8;
return 1;
+#else
+ case bc6_op:
+ /*
+ * Only valid for MIPS R6 but we can still end up
+ * here from a broken userland so just tell emulator
+ * this is not a branch and let it break later on.
+ */
+ if (!cpu_has_mips_r6)
+ break;
+ *contpc = regs->cp0_epc + dec_insn.pc_inc +
+ dec_insn.next_pc_inc;
+
+ return 1;
#endif
case cop0_op:
case cop1_op:
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