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authorTomasz Figa <tomasz.figa@gmail.com>2013-08-11 19:59:21 +0200
committerMark Brown <broonie@linaro.org>2013-08-29 17:31:02 +0100
commit9b9ae16a97e08bdc4fd5e726a4d17119dbae5d8a (patch)
tree560f45835378128d12f4c4a54365d2eb04464aec
parent06b10ff913f4d6b3e659e365ce5f70e82cca353c (diff)
downloadop-kernel-dev-9b9ae16a97e08bdc4fd5e726a4d17119dbae5d8a.zip
op-kernel-dev-9b9ae16a97e08bdc4fd5e726a4d17119dbae5d8a.tar.gz
ASoC: Samsung: Do not queue cyclic buffers multiple times
The legacy S3C-DMA API required every period of a cyclic buffer to be queued separately. After conversion of Samsung ASoC to Samsung DMA wrappers somebody made an assumption that the same is needed for DMA engine API, which is not true. In effect, Samsung ASoC DMA code was queuing the whole cyclic buffer multiple times with a shift of one period per iteration, leading to: a) severe memory waste - up to 13x times more DMA transfer descriptors are allocated than needed, b) possible memory corruption, because further cyclic buffers were out of the original buffers, due to the offset. This patch fixes this problem by making the legacy S3C-DMA API use the same semantics as DMA engine (the whole cyclic buffer is enqueued at once) and modifying users of Samsung DMA wrappers in cyclic mode to behave appropriately. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@linaro.org>
-rw-r--r--arch/arm/plat-samsung/s3c-dma-ops.c13
-rw-r--r--sound/soc/samsung/dma.c7
2 files changed, 18 insertions, 2 deletions
diff --git a/arch/arm/plat-samsung/s3c-dma-ops.c b/arch/arm/plat-samsung/s3c-dma-ops.c
index 0cc40ae..98b10ba 100644
--- a/arch/arm/plat-samsung/s3c-dma-ops.c
+++ b/arch/arm/plat-samsung/s3c-dma-ops.c
@@ -82,7 +82,8 @@ static int s3c_dma_config(unsigned ch, struct samsung_dma_config *param)
static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param)
{
struct cb_data *data;
- int len = (param->cap == DMA_CYCLIC) ? param->period : param->len;
+ dma_addr_t pos = param->buf;
+ dma_addr_t end = param->buf + param->len;
list_for_each_entry(data, &dma_list, node)
if (data->ch == ch)
@@ -94,7 +95,15 @@ static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param)
data->fp_param = param->fp_param;
}
- s3c2410_dma_enqueue(ch, (void *)data, param->buf, len);
+ if (param->cap != DMA_CYCLIC) {
+ s3c2410_dma_enqueue(ch, (void *)data, param->buf, param->len);
+ return 0;
+ }
+
+ while (pos < end) {
+ s3c2410_dma_enqueue(ch, (void *)data, pos, param->period);
+ pos += param->period;
+ }
return 0;
}
diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
index a0c67f6..9338d11 100644
--- a/sound/soc/samsung/dma.c
+++ b/sound/soc/samsung/dma.c
@@ -90,6 +90,13 @@ static void dma_enqueue(struct snd_pcm_substream *substream)
dma_info.period = prtd->dma_period;
dma_info.len = prtd->dma_period*limit;
+ if (dma_info.cap == DMA_CYCLIC) {
+ dma_info.buf = pos;
+ prtd->params->ops->prepare(prtd->params->ch, &dma_info);
+ prtd->dma_loaded += limit;
+ return;
+ }
+
while (prtd->dma_loaded < limit) {
pr_debug("dma_loaded: %d\n", prtd->dma_loaded);
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