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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-11 20:42:41 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-17 11:20:02 +0200 |
| commit | bf97b276ca04cee9ab65ffd378fa8e6aedd71ff6 (patch) | |
| tree | 70730bee7c79aaee958cb6e8d0febf546480ca6c | |
| parent | 48ecfa1090b65390b1cfa4c693ece6b171a407e4 (diff) | |
| download | op-kernel-dev-bf97b276ca04cee9ab65ffd378fa8e6aedd71ff6.zip op-kernel-dev-bf97b276ca04cee9ab65ffd378fa8e6aedd71ff6.tar.gz | |
drm/i915: implement w/a for incorrect guarband clipping
According to Bsepc, this should be set by default, but isn't. See vo1c.4
"Render Engine Command Streamer", Section 1.1.14.3 "3D_CHICKEN3"
Bspec also says that we always need to set all mask bits.
v2: Add comment about the mask bits wtf.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a9030f8..6d92054 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -497,6 +497,7 @@ */ # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) #define _3D_CHICKEN3 0x02090 +#define _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL (1 << 5) #define MI_MODE 0x0209c # define VS_TIMER_DISPATCH (1 << 6) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 813cc3c..1a6bb61 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8897,6 +8897,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); + /* Bspec says we need to always set all mask bits. */ + I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) | + _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL); + /* * According to the spec the following bits should be * set in order to enable memory self-refresh and fbc: |
