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authorFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2011-03-10 22:39:22 +0000
committerFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2011-03-12 10:22:00 +0000
commit97597a39778eefb628eb7734a18f32c7880ad0e0 (patch)
treef57989f5f90c9b28035ec41bf5769176d0b95475
parentf5b1c4b3b6d407ec5a9d93ca12738c4c7911000c (diff)
downloadop-kernel-dev-97597a39778eefb628eb7734a18f32c7880ad0e0.zip
op-kernel-dev-97597a39778eefb628eb7734a18f32c7880ad0e0.tar.gz
viafb: always return the best possible clock
Before this patch only clocks that perfectly match were used and if none existed this was not handled properly. This patch changes this to always use the closest clock supported. This should behave like before for clocks that have a perfect match but be much saner for clocks which are slightly off. Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
-rw-r--r--drivers/video/via/hw.c60
-rw-r--r--drivers/video/via/hw.h2
2 files changed, 28 insertions, 34 deletions
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 8c1393e..a7a5614 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -1677,40 +1677,36 @@ static u32 vx855_encode_pll(struct pll_config pll)
u32 viafb_get_clk_value(int clk)
{
u32 value = 0;
- int i = 0;
+ int i, best = 0;
- while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)
- i++;
-
- if (i == NUM_TOTAL_PLL_TABLE) {
- printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");
- } else {
- switch (viaparinfo->chip_info->gfx_chip_name) {
- case UNICHROME_CLE266:
- case UNICHROME_K400:
- value = cle266_encode_pll(pll_value[i].cle266_pll);
- break;
-
- case UNICHROME_K800:
- case UNICHROME_PM800:
- case UNICHROME_CN700:
- value = k800_encode_pll(pll_value[i].k800_pll);
- break;
-
- case UNICHROME_CX700:
- case UNICHROME_CN750:
- case UNICHROME_K8M890:
- case UNICHROME_P4M890:
- case UNICHROME_P4M900:
- case UNICHROME_VX800:
- value = k800_encode_pll(pll_value[i].cx700_pll);
- break;
+ for (i = 1; i < ARRAY_SIZE(pll_value); i++) {
+ if (abs(pll_value[i].clk - clk)
+ < abs(pll_value[best].clk - clk))
+ best = i;
+ }
- case UNICHROME_VX855:
- case UNICHROME_VX900:
- value = vx855_encode_pll(pll_value[i].vx855_pll);
- break;
- }
+ switch (viaparinfo->chip_info->gfx_chip_name) {
+ case UNICHROME_CLE266:
+ case UNICHROME_K400:
+ value = cle266_encode_pll(pll_value[best].cle266_pll);
+ break;
+ case UNICHROME_K800:
+ case UNICHROME_PM800:
+ case UNICHROME_CN700:
+ value = k800_encode_pll(pll_value[best].k800_pll);
+ break;
+ case UNICHROME_CX700:
+ case UNICHROME_CN750:
+ case UNICHROME_K8M890:
+ case UNICHROME_P4M890:
+ case UNICHROME_P4M900:
+ case UNICHROME_VX800:
+ value = k800_encode_pll(pll_value[best].cx700_pll);
+ break;
+ case UNICHROME_VX855:
+ case UNICHROME_VX900:
+ value = vx855_encode_pll(pll_value[best].vx855_pll);
+ break;
}
return value;
diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h
index 668d534..7295263 100644
--- a/drivers/video/via/hw.h
+++ b/drivers/video/via/hw.h
@@ -893,8 +893,6 @@ struct iga2_crtc_timing {
/* VT3410 chipset*/
#define VX900_FUNCTION3 0x3410
-#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
-
struct IODATA {
u8 Index;
u8 Mask;
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