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| author | Mikko Perttunen <mperttunen@nvidia.com> | 2014-06-18 17:23:23 +0300 |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2014-06-25 19:12:32 +0300 |
| commit | 37ab366251167cd6e517a391143db13cc2d3d65c (patch) | |
| tree | e3d535719188d7a5ecf15166f94340e7068b6f61 | |
| parent | 167d5366c4dade2f90321c7f2ef9219cbd6fedcc (diff) | |
| download | op-kernel-dev-37ab366251167cd6e517a391143db13cc2d3d65c.zip op-kernel-dev-37ab366251167cd6e517a391143db13cc2d3d65c.tar.gz | |
clk: tegra: Enable hardware control of SATA PLL
This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 637b62c..f070c36 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -110,6 +110,9 @@ #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) +#define SATA_PLL_CFG0 0x490 +#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) + #define PLLE_MISC_PLLE_PTS BIT(8) #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) @@ -1361,6 +1364,11 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; pll_writel(val, XUSBIO_PLL_CFG0, pll); + /* Enable hw control of SATA pll */ + val = pll_readl(SATA_PLL_CFG0, pll); + val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; + pll_writel(val, SATA_PLL_CFG0, pll); + out: if (pll->lock) spin_unlock_irqrestore(pll->lock, flags); |
