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| author | Dinh Nguyen <Dinh.Nguyen@freescale.com> | 2011-03-21 16:30:36 -0500 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-03-23 15:08:15 +0100 |
| commit | b6e89b21824cc37ab19e0209a7754c74d237a123 (patch) | |
| tree | edb09ba0d6ae37d6457a10fc9da0e1bce3df7c42 | |
| parent | 16f246e69b8857c6a2993f1b6663e92d4d4e5395 (diff) | |
| download | op-kernel-dev-b6e89b21824cc37ab19e0209a7754c74d237a123.zip op-kernel-dev-b6e89b21824cc37ab19e0209a7754c74d237a123.tar.gz | |
ARM: mx51: Add entry for gpc_dvfs_clk
For MX51 SRPG, we need to turn on the GPC clock in order to set the
SRPG registers.
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-mx5/clock-mx51-mx53.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index cc6ad1c..fdbc05e 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -865,6 +865,13 @@ static struct clk aips_tz2_clk = { .disable = _clk_ccgr_disable_inwait, }; +static struct clk gpc_dvfs_clk = { + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, +}; + static struct clk gpt_32k_clk = { .id = 0, .parent = &ckil_clk, @@ -1448,6 +1455,7 @@ static struct clk_lookup mx51_lookups[] = { _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk) _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) + _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk) }; static struct clk_lookup mx53_lookups[] = { |
