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| author | James Hogan <james.hogan@imgtec.com> | 2015-01-30 15:40:20 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-01-30 23:05:04 +0100 |
| commit | d76e9b9fc5de7e8fc4fd0e72a94e8c723929ffea (patch) | |
| tree | 43dfb2bb75cc269a2170b6c7b0351b7a680db301 | |
| parent | 5e32033e14ca9c7f7341cb383f5a05699b0b5382 (diff) | |
| download | op-kernel-dev-d76e9b9fc5de7e8fc4fd0e72a94e8c723929ffea.zip op-kernel-dev-d76e9b9fc5de7e8fc4fd0e72a94e8c723929ffea.tar.gz | |
MIPS: traps: Fix inline asm ctc1 missing .set hardfloat
Commit 842dfc11ea9a ("MIPS: Fix build with binutils 2.24.51+") in v3.18
enabled -msoft-float and sprinkled ".set hardfloat" where necessary to
use FP instructions. However it missed enable_restore_fp_context() which
since v3.17 does a ctc1 with inline assembly, causing the following
assembler errors on Mentor's 2014.05 toolchain:
{standard input}: Assembler messages:
{standard input}:2913: Error: opcode not supported on this processor: mips32r2 (mips32r2) `ctc1 $2,$31'
scripts/Makefile.build:257: recipe for target 'arch/mips/kernel/traps.o' failed
Fix that to use the new write_32bit_cp1_register() macro so that ".set
hardfloat" is automatically added when -msoft-float is in use.
Fixes 842dfc11ea9a ("MIPS: Fix build with binutils 2.24.51+")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.18+, depends on "MIPS: mipsregs.h: Add write_32bit_cp1_register()"
Patchwork: https://patchwork.linux-mips.org/patch/9173/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/kernel/traps.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ad3d203..c3b41e2 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1231,7 +1231,8 @@ static int enable_restore_fp_context(int msa) /* Restore the scalar FP control & status register */ if (!was_fpu_owner) - asm volatile("ctc1 %0, $31" : : "r"(current->thread.fpu.fcr31)); + write_32bit_cp1_register(CP1_STATUS, + current->thread.fpu.fcr31); } out: |
